The NEXT LAST R600 Rumours & Speculation Thread

Discussion in 'Pre-release GPU Speculation' started by Geo, Mar 1, 2007.

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  1. ants

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    EDIT: Sorry it is a repost...

    Didn't see this posted yet...

    http://www.sallandautomatisering.nl/?redirect=/content/productinfo.php?pid=34021

    Pre-order page for a Sapphire 2900XT

    Before the page is pulled the specs shown are...

    Code:
    Chipset ATi Radeon HD2900 XT 
    Memory                 512 MB 
    Memory Type            GDDR3 
    GPU clock              750 MHz 
    Memory clock           1660 MHz 
    Interface              PCI-e 16x 
    RAMDAC                 400 MHz 
    TV-out                 HDTV / HDCP / HDMI 
    Video-in               Yes 
    DVI                    2 x 
    D-sub                  No 
     
    #2741 ants, Apr 25, 2007
    Last edited by a moderator: Apr 25, 2007
  2. pakotlar

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    More like 216 vs 320 if we are using 1350mhz ALU clock and 800mhz ALU clock for x2900xtx (at 745mhz it becomes 232). Obv, this does not account for architec. differences, but on power, the x2900xt (at 745mhz) should have ~ 38% more shading power than the 8800gtx.
     
  3. Bob

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    If you're going to go though these contorsions, you might as well just count GLFOPS.
     
  4. Kaotik

    Kaotik Drunk Member
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    There's no fixed ratio, don't remember the exact mechanism, but for example GTS = 500/1200 (2.4), GTX = 575/1350 (~2.358), Dell-clocked Ultra = 650/1566 (~2.409)
     
  5. INKster

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    Scalar architectures are usually more efficient than vector ones because they can work on more than one instruction (at different stages) per clock cycle per ALU.
    The greater amount of stages also has the interesting side-effect of boosting clockspeeds at the cost of latency, but i'm no expert in these matters :D.
     
  6. Arty

    Arty KEPLER
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    I think someone here is squirming because of the impending bet loss .. :lol:
     
  7. Frank

    Frank Certified not a majority
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    Yes, you can utilize the ALUs better, because you have finer instruction granulary. And because they're simpler, you can clock them higher. But you need a lot more decoding and scheduling logic, and more buffers to keep more (but smaller) threads in flight.
     
  8. Evildeus

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    lol :lol:
     
  9. Silent_Buddha

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    Those prices are encouraging. At this rate, I wouldn't be surprised to see HD 2900 XT street for below 399 USD withing 2-3 weeks of launch at some of the places that historically price for volume rather than margin. However, I expect Newegg to price the HD 2900 XT above 399 USD as they love to wring every last cent when demand is high.

    As to what's currently been benched so far. What's there to generate buzz on? Absolutely nothing but FPS at rather low res with settings that would hardly tax a high end card.

    When I start seeing comparisons at 1920x1200 and up feating 16x CSAA (NV) vs 24x CFAA (ATI), max AF, and all eye candy on. Then I'll start to get either excited or disappointed. :p

    Plus in depth IQ comparisons. It's a given that edge AA should be basically equivalent between the two at this point. But I'm wondering if either does anything to further address transparency AA and shader AA artifacts.

    What I'm absolutely not interested in is benches of G80 or R600 with 4x or less AA and 8x or less AF. Any site that benches with no AA and no AF immediately will go onto my ignore and never visit again list. :p

    Regards,
    SB
     
  10. Arty

    Arty KEPLER
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    So there is a difference in clocks between the XT & XTX:

    XT : 750/830
    XTX : 800/1100

    Also now Fuad has changed his tune saying that XTX might not be delayed after all. :lol:
     
  11. INKster

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    Hey, he did say "Q3".
    Q3 begins on the 1st of July. There's still time, especially if the XT variant is slated to the second half of May.
    We can't be sure yet that the XTX is anything less of a "phantom edition" than the rumored 8800 Ultra.
     
  12. Geeforcer

    Geeforcer Harmlessly Evil
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    We will probably have to wait a while to learn about ALU structure of R600. I wonder if use of "320" as opposed to the count of super-scalar ALUs we've seen in the past (remember the "48 now, up to 96 some time in the future") reflects underlying architectural differences from the past previous generations or is more of a marketing response to G80s scalar ALUs.
     
  13. caboosemoose

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    Indeed. They let Anandtech do the NDA signing and then allow the holes in their non-existent chinese walls do their magic.
     
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  14. INKster

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    I had no idea "Sven Olsen" was a chinese name. :wink:
     
  15. silent_guy

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    No.
    It doesn't matter if it's scalar or vector: in both cases, you will have as many instructions in flight as there are pipeline stages. The number of pipeline stages is orthogonal to the machine being scalar or vector.

    As Frank wrote, scalar is more efficient because you won't 'waste' a part of your vector ALU when you're just executing scalar operations.

    Yes., though the latency is not really a big deal here. A deeper pipeline also increases the chances of stalls due to instruction dependencies (which can be avoided on a GPU by scheduling a different thread.)
     
  16. INKster

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    Can't those stalls be fought with greater L1/L2 cache sizes on-chip ?
    We know G80 uses at least part of a unified L2 per 16 ALU's, but i'm not certain how much of it there is, and if it's optimized to such workloads.

    The increasing use of both the R600 and the G80 as "GPGPU" processors may explain part of this strategy, because that kind of code is not exactly the same as that of graphical computations and may need more branching, therefore, more cache.
     
  17. Geeforcer

    Geeforcer Harmlessly Evil
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    The real question is, how smart/effective R600 scheduler is. If you have let's say 100 scalar operations, how will the ALUs be allocated?
     
  18. Razor1

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    many vertex calculations are vector calculations maybe thats why the geometry shaders seem to be more potent because of better utilization?
     
  19. silent_guy

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    I'm talking about cases where instruction B depends on the result of A instruction, the previous one. If the multiplier is pipelined, then it takes a few cycles for the result of instruction A to complete. As a result, instruction B has to wait.

    The longer your ALU pipeline, the higher the chance that this can happen, so your compiler has to be smart about it.
     
  20. INKster

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    So, i'd take it that the G8x architecture still has more to gain by optimizing the compiler/driver software combination than R6xx, right upfront at least.
    Am I understanding this correctly ?
     
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