The New and Improved "G80 Rumours Thread" *DailyTech specs at #802*

Discussion in 'Pre-release GPU Speculation' started by Geo, Sep 11, 2006.

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  1. ERK

    ERK
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    You expect the TMU/ALU to be clocked higher than the pixel shaders?

    ???
     
  2. Razor1

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    I'm guessing its possible just because there is an actual decrease in number of TMU's and ALU in total. compared to this gen.
     
  3. nAo

    nAo Nutella Nutellae
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    is your source saying that ROPs (blenders?) TMUs and ALUs are unified in a unique design?!?
     
  4. Razor1

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    I'm guessing from the patents about the unified ALU/TMU's, the only thing from my sources are the performance and some of the end features and power usage.
     
  5. nAo

    nAo Nutella Nutellae
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    eheh, I knew it was to good to be true ;)
     
  6. trinibwoy

    trinibwoy Meh
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    Yeah I'm still baffled. Razor what's the distinction between an ALU and pixel shader in the above quote?
     
  7. Pete

    Pete Moderate Nuisance
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    I'm with ERK. What's a "TMU/ALU," and how is that separate from a pixel shader, or able to be clocked independently of the rest of the pixel shader (given the NV40/G70 pixel shader architecture)?

    Is this what you mean about a unified TMU/ALU, or are we talking about the same thing NV's had in the pixel shader since NV40?
     
  8. Razor1

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    Well I'm guessing the TMU/ALU's are unified and decoupled from the pixel shaders. I have to find that patent any have a link? can't seem to find it will look for it later tonight.

    looking at that power point presentation. Yeah that looks to be it.
     
    #608 Razor1, Sep 28, 2006
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  9. Pete

    Pete Moderate Nuisance
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    Isn't that slide referring to something other than the TMU? I thought attribute interpolation was done with separate transistors.

    I'm also not getting that NV will share those units with the VS and PS, but rather use them in both. I'm guessing (I cannot stress this enough) NV will maintain separate "TMUs" for the VS/GS, rather than allowing the VS/GS to share TMUs with the PS.

    Edit: OK, it looks like the attribute interpolator is found on the PS, and this multi-function interpolator merely consolidates the interpolator with some other functionality that's exclusive to interpolation. You're considering the MF interp. to be (1) a unified TMU/ALU and (2) decoupled from the PS. Assuming it can be considered a TMU/ALU, then (1) makes sense. I'm not sure if (2) is specific to Xenos and perhaps irrelevant with discrete VS and PS units (as it's one-way from the VS to the PS). What I got from the thread and Hanners' summary is that, though the two transistor blocks will be consolidated into one, we'll see twice as many to alleviate the bottleneck that Deano lamented. (Though Hanners speculates that instead we'll see twice as many pixel shader units, which confuses me as I understand the bottleneck to be per PSU. Then again, I don't know if you can halve the clocks required for attrib. interp. by doubling the units, so the only solution may be to increase PSUs and their integrated interpolators. That "48 pixel processors" # doesn't make this clear to me.)

    Looking at that Xenos diagram, attribute interpolation (Shader Pipe Interpolators) seems to be separate from TMUs (Texture Pipes), that's why I'm confused by your calling this proposed MF interp unit a TMU/ALU.
     
    #609 Pete, Sep 28, 2006
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  10. Razor1

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    It might not be the same thing, have to find that patent :wink: . Jawed summed it up pretty nicely its was in a link in a thread here a few months back around the time of the g71 release.
     
  11. Razor1

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    oops didn't mean ALU's ment ROPs lol, sorry for the confusion guys! bah ok time to go out with my wife its her birthday ;)
     
  12. nAo

    nAo Nutella Nutellae
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    IIRC nvidia has at least a couple of patents were they propose to use shaders ALUs to perform blending (but it's much more complcated than that cause they read back the frame buffer within a pixel shader and there are obviously coherency problems to solve).
    They also have another patent were shaders ALUs can be used to filter texels.
    Moreover nvidia released this paper about a computation unit that should be used to approximate special functions (rcp, rsqrt, sin, log, etc..) that it's someway augmented (with a 20% area increase) in order to work as an interpolator as well (that gave us also nice indications on their future AA implementations ;) ).
    They already use (on NV4x and G7x) PS ALUs to apply perspective correction to interpolants so I would not be surprised at all if G80 will not have any custom hw interpolator at all.

    Marco
     
  13. psurge

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    nAo - are you referring to the slide where quad centers are represented by 13bit integers and the pixel centers with signed 5bit fractions? (so presumably AA will be sparse sampling from a 32x32 grid)
     
  14. Jawed

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  15. ERK

    ERK
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    That's better! :)
     
  16. LeStoffer

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    Thanks for clearly that up! :wink:
     
  17. Ailuros

    Ailuros Epsilon plus three
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    That quote from Razor is IMHLO on the right track ;)
     
  18. LeStoffer

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  19. INKster

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    More obvious news from the inquirer...
    It seems even they can't get any real scoop from Nvidia these days. :D
     
  20. Sunrise

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    Pete, Geo and Jawed like this.
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