The New and Improved "G80 Rumours Thread" *DailyTech specs at #802*

There's no way they can afford enough on chip space to store huge constant buffers, they'are gonna use a multilevel cache, bye bye constant access time to (no pun intended) contants

 

My guess is that
TCPs = Turbo Crack Pipes
VCAA = Virtually Correct AA (next-next gen will have CCAA: completely correct AA)

 

I presume you're agreeing with me, because this is why I think CBs will be maintained in memory:

• You can declare 4096 CBs
• CBs can be thousands of bytes in size
• Each shader can use up to 16 CBs
• Group constants by frequency of use

The question of latency then becomes a question of how architecturally similar they are to textures. I'd expect ATI's out of order threading to be comfortable with that, by fetching an entire buffer into on-chip memory. But a less flexible pipeline would be better off with some kind of cache as the shader is issued, rather than waiting until a CB is referenced in the code.

Notice how VB and CB are synonymous?

Jawed

 

I dont mean to pop the balloon but Nvidia themselves did say just over 500M at what i believe was a conference call. I dont know how they could "accidentally" misplace a couple hundred million only to find them a couple months later.

So we're either talking about a seperate die addition or we're reading stuff submitted by someone who just smoked a bong full of fruit loops.

 

>500M transistors in the pixel die, the rest in the geometry die

Jawed

 

Seriously, after reading those slides, my head hurts...

 

Why should you fetch an entire buffer on chip if you don't need it? doesn't make any sense.
Constant buffers will be imho accessed through very small multilevel caches, this cache memory will not be shared with texture since costants are accessed in a different way and with completely different patterns (moreover they are no filtered nor mipmapped)

yeah, they share one letter and on my keyboard V and C keys are even close to each other

 

That all just seems way too complex. We all knew that cooling and power were going to be big issues, but did we ever guess that PCB design would also get even more complex? Well, these are the same people that sorta got the V5 6000 to work...

 

There's no doubt in my mind that raw floating point power will raise considerably with the coming generation, only that I'd personally love to exploit part of it in real games than juvenile pissing contests in 3dmark06.

I guess you've missed my point entirely. Futuremarks' software can have most certainly its uses and the most scenes most certainly look beautiful, but they're in my mind an attempt to estimate what the future may hold and in that sense that estimate is not necessarily accurate.

Besides since 3dmarks are usually absolute stresstests, it would be wiser to judge future GPUs with future 3dmarks.

Well how about times less filtering optimisations on default for a change and a way more efficient AF algorithm as a simple starter? After all those years GPUs still can only filter bilinear for absolute free. I don't mind the degree, 16x samples is perfectly sufficient for my taste, as long as when an application requires trilinear (which nowadays is the fair majority) it should get trilinear.

How about less texture/shader/z etc. aliasing, moire patterns or simply put random dancing meanders in every other scene, even more so now that we're slowly moving into the float HDR era. Float HDR can be a great thing, but if you guys think we've reached a point close to perfection I'd urge to have a careful second look.

 

I don't get a thing:
8 TCPs & 128 stream processors
GeForce 8800GTX : 7 TCPs chip
GeForce 8800GT : 6 TCPs chip

What will be the chip with 8 TCP?

 

The Ultra / GTX-1024 obviously...

 

Yeah, you're right, a big CB is going to be fetched piecemeal, and needs repeated latency-hiding.

If a CB is small enough it'll fit on-die and that's the end of it (until it gets evicted ).

The sizing, latency issues are obviously amenable to the way the developer organises data in CBs. Constants exist in a flat namespace:

So, clearly, which CB a constant appears in will affect performance.

Jawed

 

So are you suggesting that the G80 is similar to how 3dlabs Wildcat III works?


Where the VSU (vertex scalibility unit) has its own 128 bit bus and the dual VPU's use a 256bit bus?




I'd figure nVidia would do somehting more along the lines of Rambus XDR


Funky vertex processor similar to 3dlabs VSU = 64bit XDR
GPU core #1 = 128 bit XDR
GPU core #2 = 128 bit XDR


So G80 would be in total 320 bit bus card.

 

Bob, you tease.

This thread just took a turn for the funny. Two separate buses, two separate dice? It's like everything NV didn't do for the past 15 years that kept them afloat and sunk others. And is 700M transistors even a realistic figure (1.5GHz is too ridiculous to contemplate, "scaling to" or not)? Arriving in November and sampled already means this is at 90 or 80nm, right? Not to mention this comes from VR-Zone. I could understand them confusing USM for USA, but the rest? And what's NV reserving the full 8 TCPs for, an "Ultra?" I thought they were still spiting us from back in the 7800GTX-512 days.

And yet....

If this is true--and there's enough in there to give me pause--either R600 is going to be equally huge and powerful, or NV's lining all their ducks up for a killing blow (can't help thinking of AMD-ATI and wondering who knew what when). I mean, this sounds like a pretty huge overhaul for a single generation, doesn't it? Even considering NV's had lots of time since NV40, going this huge is not something I expected.

And considering The Inq's latest article that 1GHz GDDR4 is sampling "perfectly" and will find its way to $200 cards by mid-2007, how does this mesh with a 384-bit bus? Surely NV can anticipate memory speeds as well as anyone else. Even if Rys is right and they planned for GDDR3 b/c of a GDDR4 shortage, are they going to move to GDDR4 with a 2007 update? I can't help myself, but 384bits of 1+GHz of DDR almost sounds like (cringe) too much bandwidth. I guess that's what these surprise 200M transistors are for.

So, were there slides at HardSpell? I can't load basically any page of their site, and VR-Zone's link to them redirects to the front page.

 

VCAA - "Variable configuration AA"? - alluding to programmable sample positions, much like ATI hardware has?

I'm hoping it's sparse 16xMSAA from a 32x32 sample-grid.

Jawed

 

Is it just me, or did the original vr-zone story just disappeared from their website ?

 

Please read the original transcipt again.

I don't see anything wrong by saying I have over half a thousand bucks if I turn out to have about 700 bucks. 700M transistors are over half a billion transistors, aren't they?