DDR-III is expected to feature short-loop through (SLT), the signaling technique debuting in some DDR-II devices to reduce noise at high frequencies. Micron demonstrated a DDR-II chip with SLT at its JEDEX exhibition booth.
SLT eliminates "stubs" that branch off to carry the signal from the memory bus to each module in the system. The multiple data lines are vulnerable to greater noise at the very high frequencies of new-generation memory chips, said Dong Yang Lee, Samsung senior product planning manager. SLT connects a series of controller drivers directly with each memory module to reduce noise and signal reflection, he said.
The technique is aimed at servers to allow the addition of eight DIMMs per channel, or four times more than with the basic DDR-II configuration.
JEDEC sources at the conference said that SLT is similar to the technique used in Rambus Inc.'s RDRAM, a bitter competitor of DDR. They said that SLT is based on designs that go back to 1970 and aren't included in Rambus' patents.
