SSDs and bit access ..

Discussion in 'PC Hardware, Software and Displays' started by DavidGraham, May 8, 2013.

  1. DavidGraham

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    Do SSDs have reduced access to their memory infrastructure? Compared to HDDs or RAMs for example? I am asking this because of their bizarre rewriting methods , Do they have less addressing capabilities compared to other conventional storage devices ?
     
  2. Colourless

    Colourless Monochrome wench
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    HDDs have internal mapping tables for just in time recovery of sectors going bad. RAM is typically accessed indirectly through page tables. The point I'm trying to make is having an indirection in place doesn't reduce access.
     
  3. DavidGraham

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    Well then , Why do SSDs have to rewrite a whole block (512KB) just to change a page (4KB) or two ? is it just for the sake of drive lifetime consideration? , or Do they have lower access to each page than HDDs for example?
     
  4. Silent_Buddha

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    It's both to mitigate the speed penalty of erase/write cycles to the NAND cells as well as to prolong the life of the NAND chip. As you go to smaller and smaller processes the endurance of NAND drops necessitating more and more efforts with regards to reducing the amount of write/erase cycles you subject each cell to.

    Micron in the M500 for example has doubled the reserve space on their Crucial drives to account for the lower endurance of NAND at the process node they are on.

    Regards,
    SB
     
  5. Grall

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    It would seem that some SSD controllers are using DSPs when erasing/writing the NAND to sense the minimum amount of voltage needed to perform the operation. This can alledgedly have a huge impact on the overall lifetime expectancy of the NAND, especially as it starts to age. I seem to recall claims of around 10x more writes to each cell before it breaks down.

    Interesting stuff. I'm really curious what a new generation of sandforce controllers might bring for example, the current ones are HOW old now again...? Weird.
     
  6. RussS

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    That's just how they're built, circuit wise. The data retention mechanism is the charge/voltage held in each cell. The individual page writes can only drain charge (i.e. change 1's to 0's).

    Adding charge is only done by refreshing the whole erase block.

    I assume the disparity between erase block and page is due to circuit complexity and density requirements. It just isn't feasible to have byte or even page addressable reset capability.

    This generally isn't a huge problem, though, and doesn't hurt you at all in big linear files, and the cost can be hidden for smaller writes through caching. It begins to generally fall apart when you start ejecting blocks from the cache due to overflow and then rewriting pages within them (for example, cycling through writing one page every block on a very big file).

    I haven't been in the industry for about 5 years, but any voltage control, etc. was inside the individual NAND chip (each NAND has its own controller). The key to speedup was managing the virtualization of pages/blocks, doing parallel writes (i.e. RAID among the NANDs), and having enough cache to hide the extremely long write erase times.
     
  7. DavidGraham

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    Thanks a lot RussS , so they do have slightly reduced addressing capability.
     
  8. migelprado

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    To compare between SSDs and ordinary spinning HDDs is probably not the right thing to do. HDD benchmarks tend to focus on the access performance characteristics that are poor with HDDs, such as spinning latency and seek time. As SSDs do not need to spin or seek to locate data, they may prove vastly superior to HDDs in such tests. However, SSDs have challenges with both reads and writes access, disk may have much better write perfomance than it would use after weeks time.
    Idealy DRAM-based SSD is considered the fastest, with average response times of 10 microseconds instead of the average 100 microseconds of other SSDs
     
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