R520: 32 PS pipelines? Any truth to this?

A 4-pipe RV530 would, theoretically, be too slow compared to a 12-pipe X800 though, wouldn't it, to be considered mid-range?

1.2GHz clock would be required for the same nominal fragment shading rate. Though if the new architecture is 1.3x more effective, then that brings the clock down to 920MHz.

Is that likely with a small die on 90nm?...

Jawed

 

Read my earlier post carefully, it wasn't entirely tongue-in-cheek (although it doesn't really relate to RV515).

 

Well, for what it's worth I think the "3" is a reference to some kind of super-sized TMU pipeline pool as per my signature - e.g. 12 TMU pipes in RV530 in a pool. Whether they're all the same type of TMU (filtering) or mixed (filtering and point-sampling) is speculation I've already got bored with.

TMU pipes should be arranged in "quads", so 12 TMU pipes could be seen as 3 quads.

I'm expecting R580 to be a 48-TMU architecture, with the TMUs arranged in a pool, again.

Jawed

 

Lots of TMU's makes zero sense.

 

If an increase in TMUs can solve texturing bottlenecks, as algorithms do more dependent texturing, then I reckon it's prolly worth having.

Jawed

 

Wouldn't bandwidth limitations negate any benefits to having more TMUs?

 

Still no guarantee that the number stands for physical units. There are also OPs.

 

If RV530 is a single pixel quad design in line with the 4-1-3-2 syntax, and runs the aforementioned TMU pool, how do we think that will stack up against the more conventional, say, 8 or 12 pipe opposition from NVIDIA?

 

No for heaven's sake. With =/>700MHz GDDR3?

 

As I said I think that "V" traditionally stands for value and thus budget. IMHO those numbers from that whitepaper where the highest and lowest configs of the entire product line.

***edit: I'm still not entirely sure what each number stands for; if I recall correctly last number is for Z/stencil and I'd guess that the "3" is ALU-OP related. There was a debate about it here in the past, but I can't recall all the details exactly either.

 

Yes, on peaks.

The way I see it, once texture data is in cache then you want to process it as fast as possible. A lot of texturing operations (high anisotropy) seem to be loop-limited, not bandwidth limited.

Jawed

 

Jawed,

While I don't recall all tidbits, the "3" is most certainly NOT amount of TMUs. Maybe Wavey will be willing to enlighten us again.

 

http://www.beyond3d.com/forum/viewtopic.php?p=484233#484233

http://www.beyond3d.com/forum/viewtopic.php?p=484235#484235

You were there!

Jawed

 

Ok I stand corrected.....for half of it. It says texture sampling abilities.

More specifically:

Yes I was there but I warned also that I don't recall all the tidbits exactly.

 

Agreed on "abilities".

A while back I hypothesised (hmm, memory alert, maybe I just thought it) that there might be 3 pools in R580:

1. filtering
2. floating point filtering
3. point-sampling

The point being that if they have these kinds of differing capabilities then it makes sense to pool them and share them equally across the fragment shading pipelines.

Much like Xenos - though apparently that's split two ways, between (presumably) floating-point filtering and point-sampling.

I see R520 as a cut-down version of this architecture - hence my sig. In R520's case floating point sampling, for example, would partially or completely bottleneck ordinary filtering or point-sampling. Hence R580's higher complexity to increase concurrent texturing capabilities.

Jawed

 

To me those numbers only make sense if they go something like:
Number of ALUs per SIMD unit/something else less important (since its all 1)/Number of SIMD units in the chip/another something else of less importance

That would make:
rv515 a single quad 4pipe card (die shrink 9600?)
rv530 a 3 quad 12pipe card (die shrink x800pro?)
r520 a single r500 style 16ALU per SIMD card (very fast clocks kinda like 9600xt had)
r580 a triple r500 style 16ALU per SIMD card (kinda a stripped down r500 presumably slower clocks than r520)

 

WTF does that mean? (I'm going nuts!)

http://vr-zone.com/?i=2487&s=1

News : GPUs & Graphic Cards : 24-pipes R520 Yield Rate at 3%


We heard that the last R520 spin at TSMC is at 3% yield rate for 24 pipes and we can certainly expect a much lower yield for 32-pipes R520. Obviously ATi is still facing some yield issues for their R520 @ 90nm process and ATI could resort to a 16 pipes R520 for better yield and make up the loss with a much higher core clock of 700MHz+ as INQ has previously suggested. It is still possible for ATi to keep to the time frame of August-September launch if decided to go ahead with 16-pipes R520. If not, 24-32 pipes R520 is expected to delayed further to Q4 this year.

 

Hey, anything to bring R580 forwards.

Please!

Jawed

 

Oy. Denmark. Old fish. Usual suspects starting to build their alibis?

I generally like VR, but it isn't all that hard to figure out what camp their main sources are in.

 

Well if there was bad news to report, don't you think it's the opposition that's going to leak it? Who leaks it isn't important, what's important is whether it's FUD or FACT.