R400/R500 guessing game

come on man ... Don't you know they just took 54 rage chips , clocked them to 2000mhz each and put them all on one card ?

 

No...it's got a roomfull of monkeys......... singing The Porpose Song!

 

And a RSWOC (Render Subject WithOut Clothes [RSN is a Matrox patent]) chip and an improbability generator (the teacup thing).


With regards
Kjetil

 

I believe it is more likely for the R400 to sport an array of vertex/pixel processors which may be subdivided and labled as "pipelines", than to sport the more conventional grouped units seen today. Something more along the likes of the NV30's vertex shader and the p10, processor pools/arrays would be more elegant than mere vliw pipelines. They could be scheduled and pipelined in any fashion. Maybe they would offer more precision by being combined (2 32-bit units for a 64-bit calculation).

 

Hmmmm......an improbability generator ...........a cup of tea...........Anna Nicole Smith......... AGGGH!!!!!!!!

<runs from room, arms waving>
screaming "DANGER WILL ROBINSON, DANGER" and procedes to pluck his own eyes out........

Jeez, just what the heck did I eat to cause that nightmare..........

 

The jump which the R400 will make compared to the R200-R300 isn't that great......... the next huge leap will not arive till R500 so till then there isn''t really that much to make a fuzz about......

The biggest diff will be R400=0.13 micron instead of 0.15 micron

 

hahahaha.. thats a good one..

 

Hehe, I gotta agree it sure is a good one

Something I've got to agree on, however, is that the R500 will be a bigger move than either R300 or R400.
That's because 0.09 is nearly 50% smaller than 0.13 - we haven't such such a reduction in years!
So, whatever companies do with 0.09, it'll be a big performance boost for sure even if there's no architectural change.


Uttar

 

What makes you so positive that graphics IHV's won't go to a .11u process before they move to .09u?

After all, ATi and nVidia both stopped at .15u in their process refinements, while Intel and AMD both jumped straight from .18u to .13u. Just because AMD and Intel plan .09u to be next wouldn't seem to lock in the conclusion that ATi and nVidia will make the same jump.

 

I'm not sure that is such a good comparison. Intel and AMD have their own fabs and constantly refine their process smaller and smaller. it's not quite so discontinuous as it appears. Their drawn process size differs greatly from the actual over time. You'll occasionally hear speculation about what their current Leff's are. Probably, at this stage of maturity their .13 process's would be better described as .11 already. I doubt ATI and Nvidia get this advantage using TSMC.

 

Point well taken, but that doesn't change my hypothesis. Rather, it strengthens it. If AMD and Intel are actually using process tweaks that give them something closer to an effective .11u (or .15u, as many claimed AMD's .18u copper process was essentially), then that supports my hypothesis that ATi and nVidia won't jump straight to .09u. Why would they, if no one else really does, and historically they have taken an "actual" in-between step wheras Intel and AMD have only taken the "effective" in-between steps?

 

I agree. I can't remember the last time ATi or Nvidia didn't use that half generation step as long as it was ready.

 

I thought I specificly read somewhere an interview with someone from nVidia, and when asked about the move to .09 micron he replied that it would be more like .11.

Those exact numbers.

 

what about those news about the partnership with cadence for the .09 process to the R500 ?

 

ATi and nVidia have very different ways of going about PCB design. I am not really at liberty to talk about it, but basically nVidia have used Cadence software for quite a while (Specctra/SpecctraQuest etc), making impedence and delay (->skew) matching of the entire system alot easier, whereas ATi use only basic PCB tools and rely on pretty tight tolerances from their ASIC teams. Once the ASICs start hitting 600MHz+ (as will happen on 0.09u, possibly even on 0.13u) they really are going to need access to the full suite of tools to keep everything ticking over nicely.

MuFu.

 

Why are the ATI cards smaller, then? R300 with 256-bit bus compared to, say, a GF 4 Ti...where would these design tools manifest themselves?
I realize smaller doesn't necessarily mean better for a card design, but getting more out of less seems that way to me...or are ATI's PCBs just outrageously more expensive to manufacture?

 

I think it's to to do with engineering headroom. nVidia like to cover their asses on a per-team basis quite a bit more than ATi and there seems to be more of a "better safe than sorry" ethos because of it. Discrete reg stages are therefore bigger, taking up board space and there are extra ground/signal layers to maintain SSTL integrity. The tools just allow them to build in this safety margin by more accurately matching impedences etc for operation at high clockspeeds. Jen-Hsun is a pretty scary guy so nobody really wants to answer to him when targets aren't met. :?

Regarding the Ti4600 board/9700 Pro boards - the former is an 8-layer PCB like the R300-942 and despite being larger, only has a 128-bit memory bus (as you say). It was designed quite a bit earlier though and even at speeds of 400/800MHz+ is not a limiting factor. It is quite obvious from the clockspeeds being reached by 9700NPs flashed with 9700 Pro BIOS's that the mem interface itself is holding things back at clockspeeds of more than 325MHz. The PCB design teams probably got an early projection for R300 at-speed (~300MHz) and then worked for a target of 325MHz or so, only verifying PCB delay and matching impedence. There was talk of ten-layer R300 boards - that was more of QC issue than anything else, with board manufacturers not being too confident that they could produce the 8 layer board reliably for a given cost.

At nVidia the PCB teams get delay/skew times from the ASIC guys and work to match the entire path from the get-go so the resulting boards have quite a bit of headroom. They had gone through three revisions of the NV30 PCB before ithe ASIC had even come back from the fab (!). I guess with the larger margins for error nVidia have more flexibility when it comes to AIB manufacturers.

MuFu.

 

BTW, at ATi they have a policy of sticking to compact designs. The board marketing manager insists on the same form factor for all the PCBs in a range - makes designing the AIW cards a bit of a nightmare but pretty cool from an eng. elegance POV. I guess they are just less bothered about it at nVidia.

The 9700/9700 Pro board is only about $5, incidently - not that expensive now that it is being produced in volume. I am told that it can quite easily qual at 350MHz+ with some resistor pack tweaks, but of course will require more power for termination because of it.