Questions concerning Clockless circuits, MIMD SPs, Shared Circuitry

Let's skip the foreplay and head for the main course right away.

1e Question: Almost all chips are synchronous designs and my question would simply be why? Clockless circuits are faster, require far less power without the need for additional power management circuitry, clock gating and other power saving techniques and also producing a lower electromagnetic signature. No more problems with clock skews, clock distribution and signal skews. Basicly lowering design complexity and freeing up some space on the die while making the chip more power efficient and faster. Why wouldn't chip makers in such a competitive market jump over to Asynchronous Circuits?

2e Question: Just how much larger are MIMD stream processors compared to SIMD stream processors (roughly)? And in which types of workloads do they (MIMD SPs) excell? Graphics? Physics? Scientific Computation? Heterogeneous computation?

3e Question: I've been looking at CPU die shots lately realizing just how small the Execution Units are compared to the entire core. AMD's Bulldozer basicly got me wondering wether it would actually be possible to share more circuitry, more specifically parts of the uncore?

That's all, for now. Every bit of explanaition is much appreciated. :smile:
 
1e Question: Almost all chips are synchronous designs and my question would simply be why? Clockless circuits are faster, require far less power without the need for additional power management circuitry, clock gating and other power saving techniques and also producing a lower electromagnetic signature. No more problems with clock skews, clock distribution and signal skews. Basicly lowering design complexity and freeing up some space on the die while making the chip more power efficient and faster. Why wouldn't chip makers in such a competitive market jump over to Asynchronous Circuits?

I guess the main reason for not using asynchronous circuits is that ports, registers etc are "read" even when their state is unstable thus propagating these inconsistent states across the chip. That being the issue, it makes it all very difficult to also test such a chip.
 
I've never designed anything with asynchronous logic, but I wouldn't say it lowers design complexity. You might remove the clock tree, but shift complexity elsewhere. Plus, clock tree designers generally do a good job. I don't recall working on a chip that was broken due to a bad clock tree. Logic bugs are much more common and I don't think clock less logic makes this any easier.

More than one company has tried to push asynchronous logic without success. There's likely a good reason for it.

Other disadvantages for async design are its not being widely taught in schools and there are more tools for synchronous design.

I don't know if anyone will give you area numbers for MIMD vs. SIMD, but with CPUs and GPUs both using SIMD you can be sure there's a benefit.
 
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