PS3: OpenGL ES V REYES V Raytracing/GI Pipelines + TBDR?

Discussion in 'Console Technology' started by j^aws, Sep 12, 2004.

?

Assuming TBDR, will the PS3 chipsets IN ADDITION also be capabale of ALL or SOME of these real-time

  1. OpenGL Only

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  2. OpenGL/REYES

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  3. OpenGL/GI

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  4. OpenGL/REYES/GI

    0 vote(s)
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  5. Anything, fully programmable!

    0 vote(s)
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  6. Other ( please state).

    0 vote(s)
    0.0%
  1. j^aws

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    [​IMG]

    Forgive me, I couldn't resist! :D Just ignore the figures in the above diagram but not the data flows and functional units! :p

    Okay, assume the above CELL chipsets (BE + 4VSs) are going into PS3 and from what we know from various STI patents.

    Given the general/flexible stream processing abilities of the above chipsets and assuming they will also be capable of tile/brick based deferred rendering (TBDR). Will the above chipsets in addition be capabale of ALL or SOME of the following real-time pipelines,

    OpenGL ES
    REYES
    GI (Global illumination) e.g. ray/path tracing, photon mapping etc.

    If not all of them then please state the obstacle(s) in the above chipsets. Thanks! :p

    PS. Also assume the APUs can access the PUs cache and the eDRAM directly.
     
  2. jvd

    jvd
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    Tbdr ?

    I highly doubt that will happen as they would infringe on a ton of pattents .
     
  3. j^aws

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  4. jvd

    jvd
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    first link has nothing to do with hdr . Did u read the thread ?
    I did not hear a mention of tbdr once let alone hdr


    the patent doesn't seem to mention anything about tbdr either .

    The thrid thread has nothing to do with tbdr or hdr either .

    You think video lodgic and that other company (gigpixel i want to say but i dunno they were bought by nvidia or 3dfx and then they were bought by nvidia ha ) would have many many pantents on this tech and i'm sure anything sony would try to use would infringe on either of thier patents .

    Also there are so many things wrong with that diagram you posted to. Many values don't add up. What are they going to cool the chip with ? a wall unit air conditioner ?
     
  5. Ailuros

    Ailuros Epsilon plus three
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  6. j^aws

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    I should've been more specific and said 'hybrid' TBDR...

    4th post by Mfa,


    The whole patent is about rendering parallel bricks and merging them to form a final image.

    Post by Jason Watkins, referring to above patent,


    Do you have any links to thoe patents, it would be interesting to compare? The SCE patents must've been submitted after those, so I'm sure they were aware of any type of infringements. ;)

    I already mentioned to ignore all the figures on the above diagram, it's there for illustration of functional units and data flows...so just ignore the figues (it's not up for discussion!) ;)
     
  7. Ailuros

    Ailuros Epsilon plus three
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    (Former) Videologic = Imagination Technologies.

    Gigapixel was an IP selling company formed from former SGI engineers, never released an accelerator to the market, lost the XBox and was bought of by the late 3dfx and belongs since the 3dfx buyout to NVIDIA.

    There are more than a few companies out there that hold related patents. Yes IMG holds patents but exclusively for their approach, which doesn´t exclude necessarily the possibility for other companies to build a deferred renderer would they want to. Trident had licensed Talisman as an example.

    IMHO the real reason why TBDR hasn´t been investigated as much so far, is most likely because the major IHVs have good reason(-s) to invest in architectures they have most experience with. They´ve neither though run into a bandwidth or efficiency wall yet and TBDR has never proven it´s real superiority this far in the high end either. Not much convincing evidence if you´d ask me.
     
  8. j^aws

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    Thanks for the link...and yeah, your right, Simon made a random comment and just vanished! :D ...So Simon F, if you'd like to elaborate on that? Thanks...
     
  9. one

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    The link at the head of this thread is this patent by EyeToy guy, Richard Marks, so it looks like the link has moved as it didn't specify the patent number. The correct patent is Image processing method and apparatus.

    For its relation to tiles

     
  10. Fafalada

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    Out of curiosity, but since when did these become realtime pipelines?

    The patent is apparently an attempt to patent layer rendering hardware. I believe that was mentioend in the first thread anyhow.

    There is a degree of analogy between dividing rendering space into layers/bricks, and dividing screen space into tiles, which is where some people derive the PS3 = TBDR link.
    There are also differencies though, one of the big ones being that TBDR products to date tile rasterization process, while the layer renderers split the whole rendering process across layer blocks.

    As for HDR, the patent goes into a fair bit of detail describing a hierarchical Z-buffer near the end :p
     
  11. Ailuros

    Ailuros Epsilon plus three
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    Could you please clarify who the author of that paragraph actually is and what he does for a living? In your place if a highly experienced engineer with TBDR (and to that with countless of patents with his name stamped on) like Simon says that the gentleman doesn´t have a clue, I´d rather insist on asking him again what he actually meant; instead of using again and again the same quote from a probable amateur.

    We´ve had tile or chunk based architectures since the original Voodoo. A simple and quite old memory optimisation doesn´t make a renderer because of that a deferred renderer, there´s more to it.

    Oh it´s a hybrid something? A little bit of this and a little bit of that then. Even today´s IMRs defer rendering via early-Z, yet they don´t claim to be TBDRs either.

    Different question: what´s the rumoured amount of raw bandwidth of the PS3, what kind of antialiasing method and with what sample density?

    Careful if the answer is anywhere near something like >50GB/s and 4xMSAA, then I don´t think we´re talking even about a hybrid anything. Just a usual IMR with clever efficiency techniques.
     
  12. j^aws

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    Ahhhhh...this is hard work! ;) ...That's the point of the poll! :p
     
  13. archie4oz

    archie4oz ea_spouse is H4WT!
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    Ok... You lost me on that one...
     
  14. j^aws

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    He's from ArsTechnica and sounded like a developer from his other posts. If you bump into Simon, then send him this way! :D ...In his absence does anyone else know what he meant?

    From the patent, it's 'tile' based alright. So it's atleast a TBR. So what's the definition of 'deferred' and 'non-deferred'? And what's a definition of anything in between? Hybrid, Semi?

    Didn't want to bring any figures into this thread...no concrete evidence of the above, so pick a figure really! :p
     
  15. j^aws

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    The Poll is whether the PS3 Chipsets above in that diagram...ignoring the figures but looking at the functional units and flows, whether you can do realt-time REYES rendering/ GI type rendering, given the flexibility of the system.

    BTW, have you seen the recent Toshiba patents found by nAo describing realtime REYES rendering?

    http://www.beyond3d.com/forum/viewtopic.php?t=15986
     
  16. Vince

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    Yes, it would be nice if nAo could edit his post and correct that as it's been a reoccurring problem in these discussions. Also, as I stated to you (One) in another thread recently, Ohba (this patent guy) was one of the prominent SCE researchers who had input into the Emotion Engine design.
     
  17. Fafalada

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    Like I said in the previous post, and pcostabel's quote explains nicely too, there are similarities between the two, but it's not the same thing. Now to clarify, I am arguing about this not because of a squabble over naming convention - but rather because I think the two terms imply different functionality.

    To start with, a tile implies separation into blocks of constant size.
    The patent implies layers/bricks of arbitrary sizes, and merging them together at different scales as required. Moreover, tile renderers don't blend tiles on top of each other, while you see that a lot with layer rendering (though it's not required, you could still arrange layers next to one another if that suits you better).
    Lastly, using layers is a pretty common technique for rendering in highend CG (most Square CG uses it a great deal for instance), and I've yet to hear anyone refer to it as "tile rendering".
     
  18. MfA

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    Call me a cynic, but I think most of those words are there just to take the attention away from this bit :

    "Thus, when the space is divided so that there are no overlapping bricks in the x,y directions, it is possible to do rendering processing similar to tiling and generate a large size final image using small high-speed VRAM area."

    Which I think in reality a system build according to this patent would be doing most of the time.

    I doubt modern PVR chips would be unable to composit 2 depth images. IMO there is very little reason to do so though, layered rendering for instance is pretty useless in games AFAICS (I dont count post processing). You dont need it for LOD anyway, the pretense that it makes it easier is one of the stupider parts of the patent. The ability to render outside a tile to slower memory can be handy sometimes (you can have some heuristics to decide to render to external memory sometimes, when that is faster than transforming the object multiple times). Not a non obvious addition though (well not non obvious to me anyway).
     
  19. j^aws

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    I agree with your definition of 'Tile' being a constant size. I also agree with your definition of 'brick' of arbritay sizes. Maybe I missed something from the patent but I see both Tiles and Bricks. The way I see that patent is that scene/screen is divided into 4 quadrants or 'tiles'. Within each 'Tile' or quadrant, overlapping 'bricks' are rendered independently. Each 'tile' is 'z-merged', then the 4 Tiles are 'combined' to form the final image. AFAIK, it's not clear from the patent whether you can split the image/scene into more than 4 'tiles' or quadrants. Am I off target here?
     
  20. Ailuros

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    That the author didn´t have a clue obviously?

    Again accelerators have been using tile or chunk based memory optimisations for eons; fairly since the advent of 3D and yes even most if not all IMRs. A deferred renderer works ideally if all scene data gets collected prior to rendering and I think the former link provided illustrates it adequately.


    But there´s "concrete" evidence of PS3 being a TBDR? I targeted and asked about antialiasing and sample densities on purpose, just because it´s one of the departments a DR has well known advantages. I recall one engineer here not long ago mentioning something about 64x sample SSAA with 64bpp HDR at 1024*768*32 for a real TBDR.
     
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