PowerVR SGX543

Discussion in 'Mobile Graphics Architectures and IP' started by argor, Jan 8, 2009.

  1. argor

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  2. argor

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    :cool: promising
     
  3. Mike11

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    Compared to what?

    So is it "just" a multi-core enabled SGX540? No other improvements (like SGX531's 128bit bus compared to SGX530's 64bit)?
     
  4. tangey

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    Its not on the IMG website yet...but heres the low-down on the SGX543...it is indeed part of a multi-core family:-

    Imagination Technologies extends graphics IP core family with POWERVR™ SGX543
    POWERVR graphics roadmap continues to outpace competition with debut of POWERVR Series5XT architecture

    Las Vegas, 8th January 2008: Imagination Technologies – the leader in semiconductor System on Chip Intellectual Property (SoC IP) – announces POWERVR SGX543, the first graphics processor IP core based on Imagination’s extended POWERVR Series5XT architecture, which enables higher performance POWERVR SGX cores and multi-processor support.

    The debut of POWERVR SGX543 takes the POWERVR roadmap to the next level. The SGX family now offers the ultimate scalability, ranging from the world’s smallest OpenGL™ ES 2.0 mobile core through solutions for performance mobile and HDTV, to high-performance gaming and computing solutions, confirming the ultimate scalability of the Series5 POWERVR SGX architecture.

    POWERVR SGX543 is the first POWERVR SGX graphics IP core available in both single core and multi-processor solutions. Imagination will release further details of POWERVR SGX543’s multi-processor capabilities at Multicore Expo 2009 in March.

    POWERVR SGX543 – the first POWERVR Series5XT architecture IP core
    The four pipeline POWERVR SGX543 is the first in a series of new SGX IP cores that utilise the POWERVR Series5XT architecture, which delivers significant enhancements to the Series5 SGX architecture used in previous SGX IP cores. SGX543’s wide-ranging architectural enhancements include:
    USSE2 - extended USSE™ instruction set with comprehensive vector operations and co-issue capability
    upgraded tile handling to further reduce memory bandwidth and improve performance for setup-bound applications
    typically 40% faster performance for ‘shader-heavy’ applications
    2x floating point and 2x hidden surface removal performance
    enhanced triangle setup delivering up to 50% higher throughput
    improved multi-sampling anti-aliasing performance
    features for optimised performance when used with POWERVR VXD and VXE video cores
    advanced colour space handling and gamma correction
    further optimised OpenVG 1.x support
    cache and MMU improvements

    The new POWERVR SGX543 delivers real-world performance of 35 million polygons/sec and 1 Gpixels/sec fillrate at 200MHz,* capable of driving HD screens with ultra smooth high definition 3D graphics. Even in a single-core solution POWERVR SGX543’s performance is unprecedented in any GPU, demonstrating Imagination's pace of innovation and ability to drive the consumer experience in graphics to levels unheard of only a few years ago in anything less than high end specialist platforms.

    Tony King-Smith, VP marketing Imagination Technologies says: “With POWERVR SGX543 Imagination continues to extend its leadership and dominance of the embedded graphics acceleration market with a solution capable of delivering blistering 3D, 2D and vector graphics. The Series5XT architecture enables us to continue to extend our dominance in mobile and embedded graphics solutions by addressing the rapidly growing demands for high performance graphics in a wide range of market segments.”

    Inside POWERVR SGX543
    The POWERVR Series5XT architecture builds on the highly efficient Series5 architecture, which ensures that maximum performance is achieved across a wide range of applications, regardless of whether the content is dominated by polygon throughput, pixel processing, high fill rate or any combination of these. Other architectures that use separate polygon and pixel processing units cannot achieve the sustained throughput or silicon utilisation of POWERVR SGX graphics cores.

    USSE2 (Universal Scalable Shader Engine2), the main programmable processing unit within each POWERVR SGX543 pipeline, incorporates a major upgrade of the data path to deliver vastly improved vector processing performance and overall throughput. This datapath upgrade is a key reason why SGX543 delivers on average 40% faster performance for ‘shader-heavy’ applications than earlier POWERVR SGX cores.

    USSE2 is a scalable multi-threaded GPU shader processing engine that efficiently processes graphics as well as many other mathematically-intensive tasks. These tasks are automatically broken down into processing packets, which can include parts of shaders, which are then scheduled across a number of hardware multi-threaded execution units for maximum processing efficiency. USSE2 is programmed using the GLSL language that forms part of the OpenGL ES 2.0 API specification from the Khronos Group.

    Imagination is also part of the OpenCL Working Group in Khronos defining the new GPGPU processing API, which will enable developers to gain greater access to the full capabilities of USSE2 in a broader range of applications.
     
  5. tangey

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    All we need now to complete the picture (!) is typical die size and power.
     
  6. Ailuros

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    I don't "understand" the reasoning myself behind the multi-core idea since I think SGX543 has "replaced" the canned SGX555 (8 pipes/8 TMUs).

    In any case one notable difference is the co-issue capability, which explains the 2x times floating point performance they claim. I have no idea what each SGX ALU is capable of, but if it should be capable for example of MUL or ADD/cycle, the 543 would then be capable for MADD/cycle (or in a more ambitious scenario from MADD/cycle to MADD+MADD/cycle).

    I've lost track after Series3 with their architectures and even more with SGX. In older more "conventional" designs like the KYRO they used to have 16 z units per pipeline if memory serves well, but no idea how it would look like on a programmable architecture slated for small form factor devices. Since they also claim twice the HSR and higher multisampling performance I'd dare to speculate that they might have increased those too.

    The better question of them all would be if that's the one that's supposed to end up in future handhelds. Multi-core though doesn't seem to make much sense here to me either.
     
  7. tangey

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    Sooo, any thoughts that a multi-core version of this core could be the ""forthcoming member of Imagination's POWERVR SGX graphics processor family." that was mentioned in the licensing announcement that is generally considered to be for the next gen PSP. ?

    The single core spec announced today is "real-world performance of 35 million polygons/sec and 1 Gpixels/sec fillrate at 200MHz"

    What level of performance would be needed/expected for a next gen PSP ?

    And finally if indeed a derivative of this is for the next gen PSP, that would allow 20-ish months from licence announcement to product in store (assuming they are aiming for Xmas 2010). That seems quite tight given the previous historic delay between licensing and product available. Especially as the nature of the product would require extensive advance stock build-up.
     
  8. Mariner

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    There's a mention of the SGX543 in Anand's first report on CES:

    http://www.anandtech.com/tradeshows/showdoc.aspx?i=3494&p=7

    The information they have about the performance of Poulsbo leads me to believe it may end up being a pretty impressive chip for the HTPC/small form factor/netbook sector, especially as the video core seems to be able to decode four h.264 streams concurrently!
     
  9. Lazy8s

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    Eight Z comparators are in, at least, the 530 variant of SGX, I think. Sixteen are used in the 543 then, perhaps?

    Giving an update to Series 5 before superceding it seems to reflect more prolific development from IMG.
     
  10. RudeCurve

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    Would a multicore configuration be feasible for use in a next generation SFF game console? How many cores would be needed to compete with a 9800GTX performance-wise?
     
  11. Ailuros

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    Sounds reasonable.
     
  12. Lazy8s

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    Assuming the boost in visible surface determination corresponds to a larger tile size, what other areas of performance are affected by using larger tiles, beside having to devote a little more silicon to the SRAM tile buffer?
     
  13. Simon F

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    Lower parameter bandwidth.
     
  14. Lazy8s

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    That's the kind of consequence on efficiency about which I'd been wondering. Thanks!
     
  15. Ailuros

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    Those interested may download the IMG Series5 XT whitepaper they've uploaded at the IMG home site.

    The triangle rate of the SGX543 is at the level I'd expect it to be (since lower than SGX540 didn't make much sense).

    What I don't understand are the fillrates of the XT line; unless SGX543 has 4 and not as formerly claimed 2 TMUs it cannot have twice as high fillrates as a SGX540 with the same amount of overdraw.

    Single chip SGX543 looks according to that whitepaper like:

    Under 65nm/200MHz with <50% shader load:

    2000 MPixels/s (w/ 2.5x overdraw?), 70M Tris/s at 16mm2

    The highest rates you'll see in that document are IMHLO for the (dual chip) SGX543MP and are simply twice as high (in theory at least).
     
  16. Arun

    Arun Unknown.
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    Why couldn't it be the quad-core variant that is quoted as 32mm2? Surely they wouldn't contradict something as clear as this in their PR... :)
    http://imgtec.com/News/Release/index.asp?NewsID=428
     
  17. Ailuros

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    Because:

    1. Read the whitepaper it states clearly 65nm.

    2. It makes more sense for SGX543 to be bigger than even 545 (look at the Series5 whitepaper its rated at 12.5mm2@65nm). Under my reasoning SGX543 ends up 3.5mm2 larger for twice the instruction throughput, twice as much Z check units, the additional YUV stuff etc etc.

    3. When you double the throughput in a USC, is it "that" normal that you end with 13% lower triangle throughput than with predecessors? SGX545 is rated at 40M Tris/s vs. that announcement mentions 35M Tris/s for the 543. Pardon but 70M vs. 40M makes more sense to me.

    http://www.imgtec.com/powervr/sgx_series5.asp

    http://www.imgtec.com/powervr/sgx_series5XT.asp
     
  18. Simon F

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    From http://imgtec.com/News/Release/index.asp?NewsID=428
     
  19. Ailuros

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    Simon a "pipeline" can mean many things. From that very same announcement:

    and for that little *:

    2 TMUs * 200MHz * 2.5x Overdraw = 1 GPixels/sec.
     
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