PowerVR Furian Architecture

So now we should count floating point output per ALU per cycle as ALU number x1.5?

 

That's.. exactly the same as I wrote, no?

Each cluster has 32 ALUs, 16 of each are MADD and the other 16 are MUL. 2*16 + 16 = 48.
1 cluster does 32*1.5 = 48 floating point operations per clock.

Clusters now have twice the ALUs, but half of them only do the multiply operation.

 

Author indicates that cores won't be in end user products until at least end-of 2018. Which raises the question, what will Apple be using in the next gen Iphone ? Same as last year with higher clocks ? rework of last year ? Have Apple already gotten the raw IP and are now designing their own graphics blocks based on Furian ?

 

One thing I've noticed is they're not saying how high the cluster count can go with Furion.
They claim Rogue could go up to 16 clusters but above 12 clusters it would lose scalability, but Furion has a higher limit. They don't say how high it is, though.
Could this scale up to 32+ clusters and match notebook/desktop-level APUs?

 

I haven't checked, but my gut instinct is that 8XT in products late 2018 at the earliest would mean a bigger gap than previously seen in IMG's high-end IP coming to market.

If true, that would suggest it's a reaction to a lack of desire from their licencees for ever increasing graphics/GPU compute performance.

Also assuming Apple is a customer that has had very early deliverables, one wonders who the other customer is who is also in at an extremely early stage (announcement cites "multiple partners)

 

eetimes article states up to 64 clusters ,although they expect not to see that initially.

http://www.eetimes.com/document.asp?doc_id=1331445&page_number=2

So working on the marketing numbers, Furian could extend to around x10 the gaming performance of a A9x at similar frequencies, assuming the bandwidth wasn't a bottleneck.

Apple might look at a high-ish cluster count Furian for future Apple Macbooks.

 

Without making any product or customer claims, there are significant changes in Furian that make it (a lot) easier for the architecture to scale up to high SPU counts. That said, really the up-to numbers are mostly marketing; if a customer comes and asks for something big and commits, we will build it, announced or not.

In the early stages of a new architecture or revision, before the RTL is final and customers have committed to licensing something, we pick a set of target cores we think are likely to be popular and start to build those. That set can and does change as the first customers get on board, and from then the roadmap is customer driven. The base architecture is configurable enough that it's practically impossible for us to build and verify every possible scaling configuration, so the customer-driven approach is necessarily the correct one.

 

I'm guessing something went wrong between your cut and your paste. I assume you intended to link to:-
https://www.imgtec.com/blog/introducing-furian-the-architectural-changes/

 

Yep, last bit of work before I disappear. If anyone has questions, please ask.

 

Baseline API support is DX10 if you take the Direct3D view of things. It's better to take the Vulkan view of things though for the base cores. There's a tessellator, for example. Peak feature set compliance is DX12.

For the same TPU count, Furian sample rate is 2x Rogue.

Geometry throughput is the same per front end, but the number of front ends is substantially different potentially, especially as the GPU gets bigger.

 

A little late but I'll try anyways.. in Rogue what was the utilization rate on the 2nd ALU and how often was it a MUL operation?