Nvidia GPU Wafer Allocations *spawn*

Well, many sources talked about 7nm TSMC's node till Nvidia launched GeForce Ampere on 8nm Samsung's.

 

Right and the majority of Ampere was planned on TSMC 7nm with Samsung for the small dies (even Jensen said it publicly). But Nvidia wanted more wafers and a better price... so hello SEC and 6-8 months delay

 

>Inter-foundry PDK downgrade and re-layout in 6mo

I need what this guy has and a lot of it.
Must be mega-potent stuff.

 

One such source was none other than Jensen himself, who pretty much lied on record in 2019 when he claimed "most of Nvidia's GPUs will still be made on 7nm".

 

Huang said that most of the 7nm GPU production will be done by TSMC while Samsung will only handling a small portion of 7nm GPU production for NVIDIA.

Well, he didn't exactly lie since 100% of 7nm GPU production is done by TSMC. He never said "most of Nvidia's GPUs will be made on 7nm"

 

Contingency plans.

 

That's not how it works.
Those are two different foundries with vastly different PDKs.
Client Ampere (including Orins) was always 8LPP.

 

Here's the actual source:

The article is from 2019, so by "next-generation" he was talking about Ampere.

 

Of course they are different. If they weren't differenz, it would not be a contingency plan, it would be idiocy. Foundry customers are already using TSMCs 3nm PDK and what Samsung offers as an equivalent (I hear tools are much less fixed there). Those guys are not sitting there with their soldering irons melting tiny transistors together. They run simulations in their design servers. And they chose from different options based on the outcome, economical aspects and desired capacity.

 

Which is the point.
No one does that.
Tapeouts be pricey as hell these days.

 

Who's talking about tapeouts? I said contingency plans.

 

Well, doesn't really matter. He is specifically talking about 7nm process products, which 100% of orders ended up being TSMC, with no Samsung 7nm being used. No lies detected.

 

Maybe he wasn't lying, just using purposefully misleading formulation. All the press got it as confirmation of using TSMC's 7nm node for GeForce Ampere. I think it's a good reason to take any similar Hopper/Lovelace manufacturing-related info with a grain of salt.

 

Read the post riiiiiiight before mine.
You don't plan shit then swap nodes between foundries in 6mo.

Meh; just ignore non-H100 parts for now.
The latter should still be Q2'22 GA.

 

While going with Samsung 8nm instead of TSMC 7nm might have sacrificed some performance, Nvidia's overall supply situation is better than AMD's on GPUs. I don't think Investors are going to complain.

 

Nobody said that NVDA started from scratch when they decided to change foundry for GeForce Ampere.
Unless someone lives under a rock, it's been multiple generations that NVDA works with Samsung and TSMC. They continuously evaluate different options in their silicon lab. Nowadays, foundries PDKs are a SYNOPIS "plugin". As a result, same generation of architectures and basically same blocks have been manufactured by different foundries (for example GP108 on 14nm SEC and GP102/104/106 on TSMC 16nm) . Obviously, process characterization like the amount of black silicon and path optimization relative to transistor electrical parameters must be adjusted. But NVDA is using extensively AI for automated physical layout for quite some time and the speedups are huge...

 

Lets track down TT's credited source:
NVIDIA Taps In TSMC For Next-Generation 7nm Ampere GPUs (wccftech.com)

then WCCTech claims it from: NVIDIA next generation 7nm process products, Huang Renxun: TSMC will still obtain most of the orders | TechNews Tech News


No primary sources; no video of the Q&A I can find, just an Atkinson serving as TechNews' IC news editor. Maybe in Chinese-realm video hosts, there is a video of the 2019 GTC China Q&A?

Either way, I'd take very little value in interpreted comments made 1 year before consumer launch, especially since the scope of the questions and answers aren't known.

 

Repitition does not reiiiiiiinforce your argument. I explicitly said, they do plan for contingency. And plans do not necessarily include a tape-out, but an RTL-File.

 

Uh-oh.

This is bleeding edge dude.
You ain't sneezing without extensive DTCO here (which in itself is a fairly lengthy merry-go-round between you, your foundry and your EDA toolchain provider).
Your freshly minted RTLs are as good as worthless here.

 

Uh-hu.

We're dealing with bleeding edge tech companies here. Don't be fooled by Jensen's kitchen setup, bro.

That why you plan, and do not scramble after shit has hit the fan.
Guess what: A borked tech for a whole generation of cards is waaayyyyyyyyyyyyyyyyy more expensive than to plan and budget ahead. Ask Intel about 10 nm if you don't believe me, or Nvidia about 40 nm.

edit:
To not make this a one-liner battle: two years between Turing and Ampere, with Turing being an addition to the roadmap. First Nvidia card officially over 300 watts. First Nvidia card with a 3-slot cooler. Ultra-dense PCB with probably a ridiculous BOM (I think you even said that yourself, don't care to look up all your one-liners though). Do you think they planned for all of this in their A-scenario? Or that they maybe had to up the specs a little more when they got wind of Navi21? And that they, being on plan B, did not have much headroom left?