NVidia Ada Speculation, Rumours and Discussion

Then why have University's like ANU who have only ever had Nvidia GPU's in there HPC clusters also going MI200? I guess not only is big government stupid but so is academia.

But also what's your point MI200 does packed FP32 and has the most HBM / bandwidth of any GPU.

 

The rumors I know are based on a slide for the australian supercomputer Setonix as reported on by hpcwire.com; the data itself has been around for much longer though. If you do the math on that one, an MI200 will be at about 55 FP64-TFLOPS, so 5x A100 w/o Tensor cores.

 

Which makes it that more mysterious since AMD did not release official specs when MI200 was announced shipping to customers on July 28, so still a lot of speculation. Unless something went wrong what's the point in keeping this from the public or potential customers?

 

https://www.hpcwire.com/2021/07/05/...-data-deluge-from-the-square-kilometre-array/

 

Yes, that's the article I linked to.

 

50PFlops is probably CPU+GPU combined though.

 

Yes, sure. At 200k Milan-cores, that's roughly 9 PFlops for the CPU (with 2,75 TFLops for a single 64core Epyc 7763) and leaves 41 for GPU.
(50-9)/750 = 0,05466 PFlops or 54,66 TFlops

 

I see. I just calculated the numbers and see you already subtracted CPU numbers out of it.
Isn't MI200 still going to be on 7nm though? I really doubt MI200 would achieve almost 5 times of FP64 performance of MI100 even if it is MCM of 2 dies if it is still on 7nm.

 

MI200 does fullrate FP64 which already quadruples the performance at the same clocks

 

Over the Matrix engine the same like nVidia with TensorCores. So general compute doesnt increase by 5x.

 

Fullrate FP64? That is kind of going opposite direction of where most of the industry is heading....hmm.

 

CDNA is paid by the goverment. Specific designed chips for one workload is nothing new. AMD doesnt need to provide better software support or even products like nVidia for selling CDNA products.

 

Almost 5 times compared to A100, not MI100. Exact number depends on final clocks.

 

it isnt 5x higher. AMD is using their Matrix engine for DP64. The same way nVidia is using TensorCores. 5x higher would be nearly 100TFLOPs.

 

Is there a source for this?

 

4x more FP64 over the compute units with a vector unit wont happen. You have to scale everything with it and alone data movement off- and on-chip will kill effciency.

 

Isn't MI200 dual chip?

 

I don't know what you find inefficient about RT. RT inefficiency is a myth. It's way more efficient than rasterization in too many cases.
As for stochastic sampling, there are great improvements in this area - importance sampling, shading caches, coherency sorting, all this improved by a lot in just 3 years.
Looking at how fast path tracing (and multi-bounce tracing) is right now in hundreds of millions polygons scenes in UE5, Omniverse, etc, it feels as if it is already here, just mix in all mentioned above improvements, add in denoising and push it to prod.

Honestly, the problem is that your average console developer treats PC as a third tier platform and unless there is an IHV involved, which would help with the workloads you've mentioned, the developer won't do anything for PC.

I don't think that's the way to go. Those SS hacks, fancy SM based area shadow techniques, compute GI, etc are just another hacks with tons of drawbacks that are layered on top of the energy inefficient computations on general multiprocessors in a time when the Denard scaling is long dead, hence the 500W monsters on the horizon.
Why bother making more of those fragile and unmaintainable systems when people can't even use existing ones properly in most cases because there are millions of tweakable parameters (apparently many devs can't even setup DLSS properly with just a few parameters).
I'd rather prefer devs and IHVs putting more time and HW effort into something way more general/unifyed and maintainable, which requires minimum tweaking and has proven to beat any hacks in CG industry.
Other than this, general/unified algorithm can live up and scale with way more efficient specialized hardware, which is the way to go in future, at least if you want to avoid 1000W monster GPUs in near future, lol.

 

So it's your assumption then.

Dual die* MCM from the looks of it.

*not counting HBM