Next NV Infomania

One more shop:
http://www.computersupplies.be/produit.php?ref=VGAXFX78GTX256

 

You know, I thought my eyes were tired last night but that first pic in nvnews thread, the one of the chip looks photoshopped. That print "on the chip" does not look believable. First the writing (isn't it always the codename of the chip?) and than if you look closely you can see edges going slightly over the surface of the chip.
I'm not calling bs on anything but simply making an observation and saying... it's a f88888g FAKE.
Or hidden on purpose. But than why didn't the maker of the thread say something about it? :?

 

They got screwed on the overclock.

 

2 x r500 surface ?

http://pic.digital-info.net/autumn/7800GTX/005.jpg

http://www.beyond3d.com/articles/xenos/images/c1.jpg

 

Did B3D get a review card?

 

You mean for SLI?

 

Well Hexus did

 

Unreleased AMD cpu too

 

http://pic.digital-info.net/sxs112/G70/sparkle5.jpg

 

Josh's latest feature suggests G70 could be 90nm -- clicky

If true, then I assume nVIDIA have finally jumped on the low-k bandwagon, although the oft-talked about clockspeeds of 430-550MHz would seem conservative, unless they are/were more FUD. What are the chances of the leaked G70 pics (the pics with mahoosive cores and burn marks) being initial 110nm G70 silicon from late 2004/early 2005, while a 90nm spin was prepped, of which we have yet to see? Too far out even for nVIDIA?

Cheers,


BrynS

 

That one really looks like a chop to me. Look at how perfectly black the GPU is compared to the memory chips, and how clear the writing is. :?

It looks like a real picture of someone measuring a GPU, but with a black overlay on the GPU itself with the fake writing.

 

The two processes are different, and chips need to be designed differently. You can't make a .90 chip from a .11 without a complete redesign.

It's like trying to build a airplane by making an airship smaller - it doesn't work that way.

 

Exactly how complete is a "complete redesign"?
What steps needs to be redone?

 

It can work if you only use functionlibs that are available for both processes. In this case you need a recompile and have the masks for the other process. The steps after the first tapeout need to be redone but thats all.

 

With new design tools like Cadence's Fabless X and Fast 16, how likely is that on chips of this complexity? Especially given that .90 is more than the .11 shrink from .13