Next Generation Hardware Speculation with a Technical Spin [post E3 2019]

Lost of studios have been are using cloud based render farms for years now. Microsoft was actually one of the first to offer this solution 9 years ago (https://azure.microsoft.com/en-us/solutions/big-compute/rendering/). Next Gen (https://www.netflix.com/title/80988892) for example was entirely rendered on Alibaba's cloud render farms. etc

 

Alright broke out the measurement taping and found out some things about Navi and the Anaconda in terms of sizes on 7nm.
5700:
GDDR6 phy controller: 4.5mm x 8
Dual CU: 3.37mm x 20
4 ROP cluster: .55mm x 16
L1+L2+ACE+Gemotry processor+empty buffer spaces + etc: 139mm

Now Anaconda:

A rougher estimate using the 12x14mm GDDR6 chips next to the SOC.

370mm-390mm.

It's a bit bigger than the 1X SOC for sure.

If we use the figure of 380mm,

75mm for CPU
45mm for 10 GDDR6 controllers
8.8mm for ROPs
140mm for buses, caches, ACE, geometry processors, shape etc. I might be over estimating this part as the 5700 seems to have lots of "empty" areas.

We have ~110mm left for CUs + RT hardware. There is enough there for ~30 dual CUs and RT extensions.

Conclusion:

The Anaconda SOC is around the minimum size you need to fit the maximum Navi GPU and Zen2 cores.

I expect Anaconda to have a minimum of 48 CUs if the secret sauce is extra heavy or 60CUs if the sauce is light.

 

There's a die shot?

 

I sure hope so, because if someone got out a measuring tape to measure the size of components on a diagram of a chip I'm gonna blow coffee all over my monitor and I just cleaned it off from yesterday!

 

You can certainly exclude geometry from ray tracing, but that wouldn't obviously be a hardware feature, or even something you could implement in hardware. That's a case of building a spatial representation (BVH) of the content you want to trace against. Once that's present, yoy can terminate and reject any rays of too great a distance in software - there's no advantage to doing that in hardware.

As mentioned in the other thread, I don't know if the spatial model could be deliberately constricted to fit a memory space (cache), and so only provide limited resolution, good enough for lighting and shadows and soft reflections, but not adequate for sharp reflections.

 

The 1.5x performance per watt of Navi is relative to 14 nm VEGA 64. The result is awful. How could AMD use the world's best 7nm process to obtain only 1.5x performance per watt???

(What I knew about transistor performance per watt: TSMC 7nm > TSMC 16nm > GF 14nm, and TSMC claims over 2.5x improvement between their 7nm and 16nm process)

Current 2019 NAVI consumes 180W TDP and only has 9.7TF, which is not suitable for consoles. I start to believe that both SONY and MS have already abandoned 2019 NAVI and using 2020 NAVI (with RDNA 2) for 10+ TF and hardware ray-tracing.

(However, how do the two companies customize their RT solution? For example, will SONY integrate AMD's and PowerVR 's RT solution?)

 

Either Navi 2 will get some more efficiency enhancements or the clocks will be conservative to reduce power metrics. PS4 and Xbone GPUs were only 800 and 853 MHz respectively when there were GHz edition GCN video cards almost two years prior. Vega has been shown to be clocked pretty high in order meet it's competition when the power sweet spot is actually a good bit lower, and no doubt people will do the same with Navi, saving oodles of power without too much performance loss.

It's almost guaranteed that the consoles will have quite a few more than 40 CUs. I'm expecting 12 TFLOPS, so something like 64 CUs (using a natively larger die if the 64 CU limit is bypassed) with clock speed to match. And 9.7 TF doesn't sound too bad if AMD is really getting a 25% performance gain vs GCN. The software optimizations (RIS especially) are nice too. These consoles will be "8K capable" alright

PowerVR's was interesting, but for the high end rendering expected in a 4K console, expect it to be in-house AMD who'll integrated it into the compute unit architecture. If they're smart, it'll be more than just an RT unit, but some kind of general SFU that does other useful things if devs want to.

 

Adjustment to my Anaconda die size, it should be around 400mm.

Damn perspective made my calc off. Someone get next to it.

 

That matches my estimate.

 

Playing rival streaming services has nothing whatsoever to do with hardware predictions. EU sanctions against hardware similarities is also so far out there to be noise. I decree it off topic just so the conversation can get back to normal technical considerations.

 

You guys are reading too much into this. Remember context, MS was not talking just to well informed techies at E3, they are adressing the mainstream public too. They were presenting broad strokes ideas.
That was just their way to say their RT is feasible for hybrid rendering, as in, a lot of the render will still rely on rasterization and traditonal rasterization-friendly shaders, but with some rays sprinkled on top for extra jazz. Pretty much something that is obvious to us, sure, but not necessarely so so everybody watching or reporting on E3. For many years, RT meant foregoing rasterization, replacing it all together, primary rays included. We know this is not happening this gen yet, but not everyone does, so MS was explaining it.

 

Nothing about it had to do with MS though.
Did you mean AMD?

The slidedeck that people are talking about is probably what went to tech press, not general public.

 

My bad, what I said still stands for AMD.
They are adressing the press, but so that the press adresses the broader public.

 

With Scarlett's APU being around 390-400m2 does that mean they can fit more CUs but have to keep clocks down?

How does that compare to say PS5 with less CUs but more clocks and both being roughly around 10% of each other. Is that a wash or more CUs vs more clocks, which one is better?

 

Higher clocks affect everything from the front-end geometry setup all the way to the render back-end (ROPs).

 

It depends on where the power @ frequency sweet spot is. Faster is better for utilization and latency, but if it takes an extreme clock to match the bigger chip you may end up with the smaller chip using more power to get the same performance. So which budget are you limited by first, your per/$$ or your per/watt?

 

Not all the press will understand it all, but for the specialized tech press they go over it and put out more technical pieces.

My point is that it's not just high level marketing material. It's pretty detailed stuff.

 

Looking at AMD's new roadmap



they probably use 7nm+.

 

I speculate that all Next-Gen Console DevKits are NOT in their Final Form and won't be until Spring 2020. What they're using now is a mix of AMD Navi GPU with separate hardware for the RayTracing aspects. They wont be assembled in a single SOC until next year when RDNA 2 hits.