New Cell patents from IBM's Gschwind: the software side :).

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http://appft1.uspto.gov/netahtml/PTO/search-bool.html

Term 1: International Business Machines ( Assignee name )

AND

Term 2: Gschwind








Now click search.


1 20040083462 Method and apparatus for creating and executing integrated executables in a heterogeneous architecture

2 20040083458 Method and apparatus for setting breakpoints when debugging integrated executables in a heterogeneous architecture

3 20040083455 Method and apparatus for overlay management within an integrated executable for a heterogeneous architecture

4 20040083342 Method and apparatus for enabling access to global data by a plurality of codes in an integrated executable for a heterogeneous architecture

5 20040083331 Method and apparatus for mapping debugging information when debugging integrated executables in a heterogeneous architecture

6 20040044880 Method and apparatus for transferring control in a computer system with dynamic compilation capability

7 20030217297 Method and apparatus for software-assisted thermal management for electronic systems



Look on Google for Alternatiff and download the /tiff plugin for your web broser ( which should be Mozilla or FireFox ).

http://makeashorterlink.com/?X1D032038

( nice picture, nice code )




Ok, here are the links ( from 1 to 7 according to the list posted above ):

http://makeashorterlink.com/?M1D162038

http://makeashorterlink.com/?V1C121038

http://makeashorterlink.com/?J1B164038

http://makeashorterlink.com/?H2A161038

http://makeashorterlink.com/?T49125038

http://makeashorterlink.com/?Z16122038

http://makeashorterlink.com/?Z44116038
 
Hey Pana, very nice find. Would you be able to do a breakdown of each patent so everyone can understand what they apply to? If you did I would be very appreciative and I'm sure the res tof the board would be also. If not that's cool, you still found these.
 
Sonic said:
Hey Pana, very nice find. Would you be able to do a breakdown of each patent so everyone can understand what they apply to? If you did I would be very appreciative and I'm sure the res tof the board would be also. If not that's cool, you still found these.

A breakdown of each patent ?

:oops:

I will try to, it will take a bit ( other posters will beat me to it, but anyways ): I am writing a .PPT presentation for a professor ( a small CELL presentation, more focused on the software side this time ) so I will put stuff from these patents most likely.
 
fxtech said:
so finally we can say that APU have EDRAM local memory , not only register , but own edram memory pool.
Local memory is (according to another patent) 128kbytes per APU and it's SRAM, not EDRAM
 
Yeah, it would be SRAM.

The local storage is the APU's system memory: the APU has to have data and instructions in it ( definition of system RAM for any system basically ).

Each APU, as nAo said, has 128 KB of SRAM as its Local Storage or LS.
 
First, Thank you for the heads-up Panajev, i'll have reading for the rest of the day. :D

Two, for those who can't see Tiff in their browser here a nice (free) plugin for tiff. http://www.alternatiff.com/

It acts like an image viewer with a lot of option.
 
Panajev2001a said:
Yeah, it would be SRAM.

The local storage is the APU's system memory: the APU has to have data and instructions in it ( definition of system RAM for any system basically ).

Each APU, as nAo said, has 128 KB of SRAM as its Local Storage or LS.

Are you talking about This figure?
 
argh.. even if it will be 128k shared from code and data will be a big step from the 16k+16k of the VU0.

but at moment we dont know anithing about the isa of the apu ,and its footprint... ..8byte for opcode + 16 for op1 + 16 for op2 ? 40byte in the worst case ?
 
Vysez said:
Panajev2001a said:
Yeah, it would be SRAM.

The local storage is the APU's system memory: the APU has to have data and instructions in it ( definition of system RAM for any system basically ).

Each APU, as nAo said, has 128 KB of SRAM as its Local Storage or LS.

Are you talking about This figure?


mmmm there are two path from mpu to the extern memory... ..who guess why ?

one with a layer cache (i immagine tha is an external cache of the mpu , and not the L2 cache) and another without
 
fxtech said:
argh.. even if it will be 128k shared from code and data will be a big step from the 16k+16k of the VU0.
VU0 is 4k + 4k, Vu1 is 16k + 16k.

but at moment we dont know anithing about the isa of the apu ,and its footprint... ..8byte for opcode + 16 for op1 + 16 for op2 ? 40byte in the worst case ?
My bets are on a fixed instruction lenght of 16 bytes, like on PS2 VUs
 
fxtech said:
argh.. even if it will be 128k shared from code and data will be a big step from the 16k+16k of the VU0.

I must say that anything might end up better than VU0 since it's at best "not what it was supposed to be" or worse it's broken. People said that it was the result of some "last minute" cutdowns in the EE architecture, others (DM) said it was because K.Kutagari hates programmers and wants them to suffer for years, looking for solution for the VU0. :D
 
nAo said:
fxtech said:
argh.. even if it will be 128k shared from code and data will be a big step from the 16k+16k of the VU0.
VU0 is 4k + 4k, Vu1 is 16k + 16k.

but at moment we dont know anithing about the isa of the apu ,and its footprint... ..8byte for opcode + 16 for op1 + 16 for op2 ? 40byte in the worst case ?
My bets are on a fixed instruction lenght of 16 bytes, like on PS2 VUs

my fault :) operand are pointer to memory or register , i have calc in the instruction foot print the lenght of the data in operand

Marco non mi hai mai detto a cosa stai lavorando esattamente..
 
fxtech said:
nAo said:
fxtech said:
argh.. even if it will be 128k shared from code and data will be a big step from the 16k+16k of the VU0.
VU0 is 4k + 4k, Vu1 is 16k + 16k.

but at moment we dont know anithing about the isa of the apu ,and its footprint... ..8byte for opcode + 16 for op1 + 16 for op2 ? 40byte in the worst case ?
My bets are on a fixed instruction lenght of 16 bytes, like on PS2 VUs

my fault :) operand are pointer to memory or register , i have calc in the instruction foot print the lenght of the data in operand

Marco non mi hai mai detto a cosa stai lavorando esattamente..

E' a caccia di ragazze... lui dice che deve fare il clipping, che deve studiare le wavelets, ma sono tutti specchi per le allodole ( le ragazze ) ;).
 
Panajev2001a said:
fxtech said:
nAo said:
fxtech said:
argh.. even if it will be 128k shared from code and data will be a big step from the 16k+16k of the VU0.
VU0 is 4k + 4k, Vu1 is 16k + 16k.

but at moment we dont know anithing about the isa of the apu ,and its footprint... ..8byte for opcode + 16 for op1 + 16 for op2 ? 40byte in the worst case ?
My bets are on a fixed instruction lenght of 16 bytes, like on PS2 VUs

my fault :) operand are pointer to memory or register , i have calc in the instruction foot print the lenght of the data in operand

Marco non mi hai mai detto a cosa stai lavorando esattamente..

E' a caccia di ragazze... lui dice che deve fare il clipping, che deve studiare le wavelets, ma sono tutti specchi per le allodole ( le ragazze ) ;).

ok è piu o meno come il mio lod dinamico nel 1999, alla fine funzionava pure , ma ciucciava piu cpu lui che riproiettare la mesh completa :) , solo che avevo la testa altrove per accorgermene..

wavelet correlate a cosa? l'unico approcio per cui le userei io è per una qualche forma di compressione delle texture , solo che tutti ci provano e nessuno ne trova uno scopo pratico funzionale.

Cambiando argomento , credete che PS3 avra metodi di rendering HDR ? dovremmo ipotizzare un frame buffer a 64bit.. i hope
 
Me is gonna kill Panajev :)

PLEASE..use english as board language, or use PM
 
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