In general, the faster data can be retrieved, the faster the host processor can execute its algorithms. Internal parallelism on the processor side requires ever-faster data-transfer rates from external memory to keep parallel execution units active. In the DRAM world, this has translated into the move from single-data-rate synchronous DRAMs (SDRAMs) to double-data-rate (DDR) SDRAMs down one path and to the use of Rambus' DRAM (RDRAM) down a second path. A third fork for specialized low-latency applications, such as that found in network subsystems, has produced a reduced-latency DRAM (RLDRAM) that's optimized for real-time packet-handling subsystems.
Already, the first-generation DDR interface, which peaked at 333 to 400 MHz and memory densities of 512 Mbits (although at least one company is sampling 1-Gbit devices), is giving way to the second-generation version, DDR II, which offers data-transfer rates starting at 400 MHz. Over the next two years, DDR II data rates will peak at 667 to 800 MHz, and available memory densities will increase from today's 256- and 512-Mbit devices to 1 Gbit/chip. A third-generation DDR interface will offer still higher data rates. However, samples probably won't be available until late 2004 or early 2005.
Yet many designers still look for even faster data-transfer rates. Answering that demand, several companies developed new memory-interface architectures that promise to boost transfer rates to more than 6 Gbytes/s. Later this year, Toshiba and Infineon Technology both expect to sample DRAMs based on Rambus' extreme-data-rate (XDR) interface.
The XDR approach requires a full revamping of the DRAM interface and a new point-to-point memory subsystem that may take a while to be accepted by mainstream systems. Another approach, slated for introduction this quarter by Silicon Pipe Inc., employs a controller chip that sits between the host processor and the memory array and multiplexer chips that connect the controller to the memory array. This scheme, which can use standard DDR memory DIMMs, achieves throughputs of up to 12.8 Gbytes/s.
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LOOK FOR A HIGH-SPEED MEMORY interface from Silicon Pipe as an intriguing alternative to the XDR interface. The novel interface design employs a controller that converts the parallel bus of a host system to serial interfaces. In turn, the interfaces connect to small multiplexer circuits that talk to standard DRAM modules.
