load instruction alignments

Discussion in 'CellPerformance@B3D' started by c94wjpn, Dec 17, 2007.

  1. c94wjpn

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    I am looking at some assembly code for loading registers on the spe, and I find that there are three useful load commands, and they seem to offer different alignment capabilities:

    lqa will load a quadword from a 4-byte aligned address
    lqd will load a quadword from a 16-byte aligned address
    lqx will load a qw from a 1-byte aligned address

    is my documentation correct? I am surprised that there is no alignment demanded of lqx (which sums two registers to give an address).
     
  2. Npl

    Npl
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    you can specify nonaligned addresses, but all load/store instructions will zero out the last 4 bits.
    eg you can request a load from address 7, but you will get the quadword at address 0.
     
  3. Graham

    Graham Hello :-)
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    While we welcome all members and their questions, we do not welcome the attitude you have shown in your reply.
    Please remember that people here are trying their best to help you, when they are under no obligation to do so.

    Have a nice day.
     
  4. patsu

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    Graham, I think Sousuke questioned c94wjpn's documentation source. It seems that there are discrepancies between their versions. Might be good to lay it out just in case.
     
  5. popper

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    http://www-01.ibm.com/chips/techlib/techlib.nsf/products/Cell_Broadband_Engine

    http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/30B3520C93F437AB87257060006FFE5E/$file/Language_Extensions_for_CBEA_2.5.pdf 09/14/07


    12 SPU Low-Level Specific and Generic Intrinsics


    ...
    si_lqx: Load Quadword (x-form)
    An effective address is computed by adding word element 0 of quadword a
    to word element 0 of quadword b and forcing the 4 least significant bits to
    zero. The quadword at this effective address is then returned in quadword
    d.
    d = si_lqx(a, b) LQX d, a, b

    ...


    http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/EFA2B196893B550787257060006FC9FB/$file/SPU_Assembly_Language_Spec_1.6.pdf 09/03/07

    Instruction Set and Instruction Syntax
    ...
    lqx rt, ra, rb
    Load quadword (x-form). A quadword is loaded into register rt from the effective address computed by the sum of registers ra and rb

    ...
     
    #5 popper, Dec 18, 2007
    Last edited by a moderator: Dec 18, 2007
  6. patsu

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    c94wjpn , would you be able to share some of your work that may be commonly needed ?
     
  7. Vitaly Vidmirov

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    c94wjpn:
    all the instructions you mentioned has 16-byte alignment
     
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