International Solid State Circuits Conference

Discussion in 'Console Technology' started by McFly, Feb 17, 2004.

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  1. McFly

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    Looks like the news from the conference are coming in:

    http://www.macworld.co.uk/news/main_news.cfm?NewsID=7942

    So maybe the PSP 12 hour gaming rumor was more then just a rumor.

    I'm sure EETimes has more about it soon, so post if you found something. Edit: http://www.eetimes.com/semi/news/OEG20040216S0007

    The Teraflop CPU again. ;)

    Fredi
     
  2. V3

    V3
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    Didn't know people here actually interested in ISSCC

    http://www.elecdesign.com/Articles/Index.cfm?ArticleID=7123
     
  3. V3

    V3
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  4. Panajev2001a

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    Interesting news.

    So, Sony has three e-DRAM blocks recently co-developed: one with Toshiba ( ASC9 ), one with Mitsubishi and now this.

     
  5. Deadmeat

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    ...

    Is the PSX3 launching in 2010??? I didn't know.
     
  6. McFly

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    Re: ...

    2006 is before the end of this decade, too. ;)

    Fredi
     
  7. London Geezer

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    Re: ...


    Still quoting what you think will make some people look bad in the eyes of other people...

    Why did u not include the full sentence, which was:


    Is that PS3? Don't think so...
     
  8. nobie

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    Certainly memory that fast won't be in PS3.
     
  9. hey69

    hey69 i have a monster
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    hm, my brother left past saturday for this conference to SF... didn't knew that conference would end up here in a thread..
    will ask him out about the details when he returns
     
  10. Deadmeat

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    ...

    According to Moore's Law

    CELL@Winter 2009 = 1024 GFLOPS
    CELL@Summer 2008 = 512 GFLOPS
    CELL@Winter 2006 = 256 GFLOPS
    CELL@Summer 2005 = 128 GFLOPS

    So you get a Max 128 GFLOPS processor in PSX3. I was right......

    MS has nothing to fear from PSX3; it just need to watch its cost, make sure components perform as specified, and developers get a good head start.
     
  11. Panajev2001a

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    Re: ...

    You are pulling stuff completely out of your ass to prove that a claim you pulled from the same orifice was right.

    :roll:

    Psst... even in your world of fantasy ( which is a different one from what we know as reality [in my version fo that place I once wished for even more FLOPS... well guess what we are both going to be wrong probably] ), PlayStation 3's CPU would have 256 GFLOPS as the machine will not be out before 2006.
     
  12. Deadmeat

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    Unless Kuataragi and co beats Moore's law as they claim to have in the past....

    If the 256 GFLOPS silicon becomes available in winter 2006, then the console itself will not be available until summer 2007. There is a 6 month gap between the silicon availability and the system availability.

    So the PSX3 CELL(I prefer to call it "Emotion Engine 3") has to enter mass production by summer 2005 to make the Xmas launch of 2005 or January launch of 2006. And certainly the CELL that Kutaragi Ken will demonstrate this spring will be doing around 64 GFLOPS.
     
  13. Fafalada

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    Ok, this one I am definately keeping this for future reference.

    Eh? Backpedalling one post after such self assurance? You said "WAS" right, doesn't that mean that you've been to the future already and have seen it all?
     
  14. Panajev2001a

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    How about 256 GFLOPS Broadband Engine by Spring 2006 ? That would be enough for a worldwide ( Japan and United States ) launch before Q4 2006.

    Can you please call it PS3 ( as Trademarked by SCE ) or PlayStation 3 ?

    Since we have an official PSX and the PS-X Trademark by SCE has been dropped ( DEAD ), please go by PS3 or PlayStation 3.

    Also, the CPU is called BE or Broadband Engine.
     
  15. Vince

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    Re: ...

    Deadmeat, stop being a f*ing idiot. Moore's Law is a rough bound which describes the decrease in transistor size as plotted against time. Thus, we can use some of that math stuff and state that if the size shrinks by a factor 1/N at t+1, and we hold the aggregate area constant we can fit N times more transistors at t+1 than at t.

    And as for how 1TFlop can be explained, logically we're lead to conclude that you can hold more logic per static area as time goes on. We can also state that it just might be, maybe, that FLOPS are a nonlinear function of aggregate logic count. Meaning that in designing an IC like the EE at 250nm, there was a necessary and fixed proportion of the the allowable tranistor budget that's devoted to non-FLOPS producing constructs. There needed to be a DMAC, a MIPS core, etc. These were all mandatory and took up a substantial portion of the allowable budget and because of this you got just 8 FPU's per static construct/core.

    When you move to 65nm, you get this massive influx in logic potentiality. And due to the massive influx in logic, the fixed functionality remains relatively constant from the EE to the BE and is now but a small faction of the total area, thus allowing the bulk of the new logic to go toward producing your Flops. Thus we now have 32 FPU's (+32 FXUs) per static construct/core. The influx is enough to further add multiple core/PE's and add to this the process technology advancements(sSOI, Low-K, 65nm, etc), logic effeciency and clock speed grains (Even the massive I-32GS clocked at 600MHz @ 180nm) and you get the patent.

    Visually this concept looks like (Note: the line sizes aren't absolute, their relative to the total allowable for each process stepping and the lines are relative proportions):

    Code:
    Emotion Engine (250nm)
    
    Total Logic Budget:
    -------------------------------------------------------------------------------------
    
    Logic for fixed functions:
    ----------------------------------------------
    
    Logic for FPU/FLOPS:
                                                  ---------------------------------------
    
    
    BroadbandEngine (65nm)
    
    Total Logic Budget
    -------------------------------------------------------------------------------------
    
    Logic  for fixed functions:
    -----------
    
    Logic for FPU/FLOPS:
                --------------------------------------------------------------------------
    In conclusion, FLOPS in this case are a nonlinear function of Moore's Law. Goddamnit, now I'm late. See what you're stupidity does.
     
  16. Deadmeat

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    ....

    You are asking too much.

    PS. I was reading gameonline.co.jp's rumor section and has it that PSP is rumored to be downgraded. Apparantly the upper management(Kutaragi) asked for an unrealistic spec that the engineers couldn't meet and the final spec had to be cut down.
     
  17. notAFanB

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    interesting, details please
     
  18. Panajev2001a

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    There have been some rumors about WiFi and MP3 playback being present but not activated until a post launch Firmware release and he is simply running with it while blowing it out of proportion.
     
  19. Guden Oden

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    Re: ...

    That could have been true, perhaps, had:

    A - Moore's so-called law (which it isn't) been a measure of performance increase over time (which again, it isn't), and:

    B - "the end of this decade" meant "winter 2009", which I'm sure the original quotee would have said if that was what he meant.
     
  20. Fafalada

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    There aren't any, it's a rumour without any actual hint about WHAT is supposed to be downgraded.

    Of course, in DMs world the PSP is now downgraded for all eternity to come - it is completely irellevant if the rumour prooves true or not, as far as he's concerned it already happened.




    SPEAKING of which...
    DM, I've got another interesting rumour for you. Apparently GS3 will have HUGE fillrate, but only when drawing Green pixels.
     
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