Intel Xe Architecture for dGPUs

Discussion in 'Architecture and Products' started by DavidGraham, Dec 12, 2018.

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  1. Bondrewd

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    This isn't how you do it this year buddy.
    A-ha.
    Gen12LP has no hardware RT.
    Gen12HPG is ?????? for the featureset.
     
  2. Lurkmass

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    Also I'm not sure what the big deal is behind a VLIW architecture when there's strong possibility that Kepler and Maxwell/Pascal were technically VLIW architectures as well since they required explicit encoding to dual-issue instructions ...
     
  3. Jawed

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    I strongly believe this is bullshit. I expect NVidia to prove this by the end of 2022, perhaps 2021.

    It's a mess when your architecture is wrong. Similar to how asynchronous compute is a mess when your architecture is wrong.

    Doesn't NVidia do multi-instruction issue? Doesn't the compiler produce multi-instruction bundles for max throughput?
     
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  4. Bondrewd

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    No, AMD will do it, next year, for both client and DC because they feel like it.
    You also need some very very delicate and nice packaging there.
    Yes and yes.
     
  5. techuse

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    Navi is 4 yes? What is Turing/Pascal?
     
  6. Rootax

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    So maybe, all in all, they are ok with soft scoreboarding from their experience with Gen11 ?

    For the dx12u features , yes, It's not cool, but I don't believe it will mater a lot for a first design. And they still support VRS Tiers 1.

    For me, they don't need to be perfect yet, they need to release the product, with good performances and good drivers. If they do that, it's already a big achievement imo. Then, of course, they need to improve, like AMD and nVidia...
     
  7. trinibwoy

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    Was Pascal dual-issue managed by the compiler?
     
  8. DavidGraham

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    Turing is 6, same as Pascal. Also Navi/Vega are 4 but only in special circumstances If I recall correctly.
     
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  9. techuse

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    What do they fall back to? Do you have any info on the circumstances?
     
  10. Lurkmass

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    It depends mostly on how clever the programmer is with the hardware. If they understand the conditions/constraints (restrictions) behind dual-issue instruction scheduling then it's possible for the compiler to generate codegen for these dual-issue instructions ...
     
  11. Malo

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    I thought Vega was 4 and "up to 17" based on the use of their primitive shader? (which obviously never came about)
     
  12. DavidC

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    That's from the Anandtech article analysis?

    Well they updated it:
     
  13. Digidi

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    2 Rasterizer for 768 Shader?... this ich much.

    the question ist how much Polygons can the Frontend accept. We know after backface culling it can rasterizer 2 Polygons but how much polygons is it able to cull?
     
  14. Ryan Smith

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    Yep. Leave it to Intel to completely overhaul their geometry front end for parallel execution, and then not bother telling anyone.:lol:

    The upshot, at least, is that their technical team is paying attention to what's being written. So if we get something wrong, they've been giving us the correct data.
     
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  15. trinibwoy

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    Does anyone even benchmark raw triangle throughput anymore? I think the last was hardware.fr. Damien is sorely missed.
     
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  16. Ryan Smith

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    Most of the tools for this are quite old these days, as low-level benchmarks don't garner the interest they once did. Unfortunately, I'm not sure what Damien was using to begin with.
     
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  17. trinibwoy

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    Yeah that’s understandable. Times have changed. It’s not even clear whether geometry throughput has a material impact on overall game performance these days. Maybe someone will write a mesh shader bench.
     
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  18. techuse

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    Doesnt seem to be too important given how well GCN compares to NV in most AAA games. This could be way too simplistic a view though.
     
  19. Digidi

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    #259 Digidi, Aug 16, 2020
    Last edited: Aug 16, 2020
  20. 3dcgi

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    I interpreted the quote to say they can call two primitives per clock meaning they likely rasterize one that survives culling.
     
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