Intel Xe Architecture for dGPUs

Discussion in 'Architecture and Products' started by DavidGraham, Dec 12, 2018.

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  1. Silent_Buddha

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    Considering that diagram is for an integrated GPU, I don't see where HDMI 2.1 could come in useful other than possibly VRR support which they could still implement in 2.0b if they wanted (like NV currently). 4k/120 or 8k aren't usage scenarios that are likely to see widespread adoption for laptop users using integrated graphics. People that want 4k/120 will mostly be "core" gamers who are going to buy a gaming laptop anyway.

    HDMI 2.1 would be nice, but it's not exactly needed for integrated yet.

    Regards,
    SB
     
  2. no-X

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    Rocket Lake is a desktop product. It supports AV1 (codec developed for 8k video), but doesn't support 8k HDMI (HDMI 2.1). So it can decompress 8k video, but it can't send the 8k stream to the display.
     
  3. tuna

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    AV1 can (and will) be used for any resolution video. Everybody* will probably be using it in a couple of years.
     
  4. Silent_Buddha

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    Considering that 4k is still not common on desktop and 8k monitors are extremely niche at the moment, It's likely that for any desktop user that desires 8k video, they aren't going to be interested in using the integrated GPU.

    That'll obviously change over time, but currently 8k consumers of PC monitors will generally be people with very specific needs.

    Regards,
    SB
     
  5. DegustatoR

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    You can have 8K output at 30Hz on a DisplayPort 1.4a connection with DSC.
     
  6. no-X

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    Most TVs aren't equipped by DP. Anyway, does Rocket Lake support DP1.4 with DSC?
     
  7. Kaotik

    Kaotik Drunk Member
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    AMD and NVIDIA might just aswell pack their bags and leave :runaway::razz:

     
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  8. xpea

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    [​IMG]

    That's huge :runaway::runaway::runaway:
     
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  9. Kaotik

    Kaotik Drunk Member
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    "This tweet is unavailable".

    I'm guessing Ponte Vecchio?
    Going by the Intel slides, it needs to be huge, that thing is supposed to hold 8 Compute Nodes and 4 RAMBOs and bunch of HBM
     
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  10. manux

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  11. Kaotik

    Kaotik Drunk Member
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    They've reposted the GPU image, but left out the others with Koduri & Keller and someone I don't recognize
     
  12. Dayman1225

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    Likely due to the fact that the face masks were not being used correctly. (Keller wasn't covering nose, Raja has a beard which means the mask can't create a seal.)

    As for the chip it self, it is likely PVC because those real chips look a lot like the renders for Aurora..[​IMG]
     
  13. Kaotik

    Kaotik Drunk Member
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    Yep, it does, so it should have inside 8 Compute Nodes, 4 RAMBOs and unknown amount of HBM stacks two portions with 8 Compute Nodes, 4 Rambos and unknown amount of HBM stacks each, bunched together with EMIBs and Foveros.
     
    #213 Kaotik, May 1, 2020
    Last edited: May 1, 2020
  14. TheAlSpark

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    Maybe 4 chiplets?
     
  15. Kaotik

    Kaotik Drunk Member
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  16. Dayman1225

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    So I don't think it is PVC. Ponte Vecchio is based on Xe HPC, but Raja referred to this chip as the "bapp of all"


    Which he originally referenced back in December when talking about Xe HP.


    So I think this chip is Artic Sound or some other Data Center dGPU, not Ponte Vecchio
     
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  17. Kaotik

    Kaotik Drunk Member
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    That package is around 81x53mm, that's ridiculously big - pretty much certainly too big for anything but a HPC chip. It's size and shape also fit the Project Aurora illustrations Intel did pretty well (yes, illustrations are just that, not necessarily accurate etc, i know)

    Also, the HPC variant was a "afterthought" to begin with, maybe the HP team handles that too and was referring to it with the baap of all rather than consumer Xe-HP part

    edit: also, I'm not sure if bfloat support is something you'd need in consumer product, but on HPC side it's very useful, note the Raja's "b-floating" reference
     
    #217 Kaotik, May 1, 2020
    Last edited: May 2, 2020
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  18. del42sa

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  19. Kaotik

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    It's Xe-HP datacenter variant after all in that picture, not Xe-HPC Ponte Vecchio
     
  20. DmitryKo

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    Could these boards employ the much-publicized Omni-Directional Interconnect (ODI), which combines silicon interposer (Embedded Multi-Interconnect Bridge, EMIB) with 3D stacking (Foveros)?
    https://www.extremetech.com/computi...irectional-interconnect-combines-emib-foveros
    https://fuse.wikichip.org/news/2503...together-adds-omni-directional-interconnects/
    https://fuse.wikichip.org/news/3508...l-3d-packaging-tech-gains-omnidirectionality/

    AMD and NVIDIA are supposed to use the TMSC CoWoS interposer for HBM-based products.
     
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