Intel Embedded Multi-die Interconnect Bridge

Grall

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Just noticed this interesting Hot Chips conference over at Anandtech: http://www.anandtech.com/show/11748...-stratix-10-fpga-live-blog-845am-pt-345pm-utc

It's about enabling very low-power, high-performance wide I/O between dies in multi-chip modules without needing to use silicon interposers. Essentially - from what I can gather - the tech essentially embeds small silicon bridges into a standard laminated substrate, positioned between the dies of an MCM. This way you can achieve the high-density I/O of a silicon interposer, but without running into size limits associated with the same.

It probably goes without saying that the precision required when manufacturing and assembling these joint packages has to be immense, but Intel says the tech is already mature and out in the wild, so it's apparantly viable!

Haven't seen any discussions on this technology yet, maybe someone will find it interesting.

Seems Intel wants to keep this tech for themselves by the way, so it may not do much good for either AMD or NV. *shrug* :D
 
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