Intel ARC GPUs, Xe Architecture for dGPUs

Discussion in 'Architecture and Products' started by DavidGraham, Dec 12, 2018.

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  1. Kaotik

    Kaotik Drunk Member
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    So apparently GamersNexus decided it's ok to post a video filled with slides which show the NDA hasn't expired yet
     
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  2. BRiT

    BRiT (>• •)>⌐■-■ (⌐■-■)
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    Is it safe to assume he was not under NDA but got the slides through other leaks/means? Or did someone else start the leak so once it's already public they can talk about it?
     
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  3. Kaotik

    Kaotik Drunk Member
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    VideoCardz leaked some stuff, haven't checked if it covers all the same as GN video, but VC watermarks their slides so at least GN isn't using them
     
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  4. Bondrewd

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    It's already inside of bunch of other shims like Proton so probably?
    I guess.
     
  5. So could it run on a pair of Cadence Vision C5 matrix accelerators for a 720p output?
    :devious:


    The slides say 6 a.m. Pacific of August 19. Wasn't that >1h ago?
     
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  6. pharma

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  7. Bondrewd

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    Ha!
    No, needs proper maff support.
    But AMD will flay their WGP into a skinny ML acc only duty at a later date.
    19m ago.
     
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  8. Kaotik

    Kaotik Drunk Member
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  9. PSman1700

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  10. DegustatoR

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    [​IMG]

    The pairing in the image is interesting.
    Are they 8 wide or 16 wide in h/w?

    In any case seems narrow for a modern GPU.
     
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  11. Bondrewd

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    They're just 16EU subslices.
    I.e. 128ALU per Xe Core.
     
  12. So XeSS is confirmed to be cross-compatible with other GPUs, being able to run through DP4a, and it uses motion vectors like DLSS.
    Great news.


    [​IMG]

    [​IMG]
     
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  13. DegustatoR

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    https://www.anandtech.com/show/16895/a-sneak-peek-at-intels-xe-hpg-gpu-architecture

    Seems about what you'd expect from a 3070 level card.
    Next year will certainly be interesting.
     
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  14. troyan

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    Great news for DLSS actually. Still dont know how Intel want to provide DP4a support without an API support.
     
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  15. Granath

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    From GN
     

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  16. PSman1700

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    Yes seems Intel's following in Nvidia's footsteps.
     
  17. DegustatoR

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    If it's SYCL then it will run on OpenCL/CUDA/OneAPI/whatever AMD has.
     
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  18. fellix

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    The vector unit has the same rate for FP32 and FP64 FMA op's, but double for FP16. Does that mean there is a separate FP64 pipeline alongside the FP32 one that probably serves the packed FP16?
     
  19. CarstenS

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    I bet that's what the cracks did. Or something along those lines. :D
     
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