I Can Hazwell?

Discussion in 'PC Industry' started by Grall, Nov 9, 2011.

  1. Zaphod

    Zaphod Remember
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    Off topic:
    I had (may still have - somewhere) the followup. The very first computer I bought with my own money. Could only afford the "cheap" (probably north of ~$3K in today's prices) grayscale version, but what a glorious little machine that was!

    [​IMG]
     
  2. Blazkowicz

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    True but I want buttons to type on, including ctrl, !, $, \, |, *, }, <, >, à, home, end.
    I don't like these little thingies where I don't feel like I'm in control and I can only finger things, try to scroll a lot by swinging my finger wildly, and try random stupid things like talking into the device or shaking it. Then I get lost : I end up on the phone's main screen and crap, how do I get back to the web page I was on? :lol:. It's like I have no idea what I'm doing. Also, $DEVICE is stuck at Android 2.x stuff like that, and I don't want to have a google account. And crap, that little spyware game will maybe take pictures of me in my underpants and upload it somewhere without me knowing about it.

    Hell maybe I'm stuck in the nineties and early 00s, where a command line was expected in a consumer OS (now kids tell me shit like "you're programming?" and I have to tell them "no, I'm *using* the PC", really, back then it was grandpa stuff to be clueless about this), and when the media would lecture us about not giving our personal information away on the internets, including real name, birth date etc.

    End rant.
     
  3. Rodéric

    Rodéric a.k.a. Ingenu
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    Sooo, say I want an Haswell with DDR4 support and no embedded GPU, what would be its name and when would it be released ?
     
  4. Albuquerque

    Albuquerque Red-headed step child
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    Pretty sure you're looking for Haswell-E on the Wellsburg chipset (successor to x79.) That gives you Haswell with 6 or 8 cores, no multiplier lock, no IGP, and quad-channel DDR4.

    You'll be waiting until at least 2Q 2014 if you believe some of the iffy rumor mill. I wouldn't hold my breath...
     
  5. Lightman

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    I'm 50/50 between wanting to jump into future and discover all the tech. advancements vs. living in early 90' where we had PC's, Amiga, Atari and setting up OS meant writing startup-sequence scripts and Dos(Norton)Navigator was a blessing on PC :grin:.

    Sorry for OT!!
     
  6. Grall

    Grall Invisible Member
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    Bluetooth (or USB) keyboard...

    You spend money on underpants, but rather buy a 80186 laptop from the friggin 1980s? Go commando; you can afford better electronics that way! :lol: (Oh, and by the way, stay away from "free" android games. Always advisable, even if you are actually wearing underwear, AND pants too for that matter...)
     
  7. Gubbi

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    The Athlon and derivatives can reorder loads with other loads and with stores with known addresses. It is equivalent in capability in this regard to Intel's PPRO/P2/P3/P4 and Core.

    Cheers
     
  8. Rodéric

    Rodéric a.k.a. Ingenu
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    Ok, ty :)
     
  9. Raqia

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    My source was anandtech:

    http://www.anandtech.com/show/1998/5

    "In contrast, the Athlon 64 can only move loads before independent ALU operations (ADD etc.)."

    It does say this:

    "Once Loads and Stores are in the queues of Load/Store units, the Athlon's L/S unit allows Loads to bypass Stores, except of course when the load would bypass a store to the same address. Unfortunately, by then the Loads are already out of the ICU and cannot be used to fill the holes that dependencies and cache misses make. You could say that the Athlon (64) has some Load/Store reordering but it's much later in the pipeline and is less flexible than the P6, P-M, and Core architectures."
     
  10. Gubbi

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    Almost certainly incorrect. Here's a PDF from 1998 giving an overview of K7's capabilities. Page 4 mentions aggresive memory reordering.

    Cheers
     
  11. Raqia

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    Got it, thanks for that. I do like that Anandtech makes an attempt to delve into the details of the products that they review, but they're often inconsistent with more serious sources like journals and realworldtech. For instance their conclusion re: Sandybridge:

    http://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/9

    doesn't seem to have caught onto the rather major changes to architectural underpinnings. Compare this to David Kanter's:

    http://www.realworldtech.com/sandy-bridge/10/

    or Andy Glew's:

    "Sandy Bridge is what P6 version 2.0 should have been.
    It's the first new OOO core from Intel, designed by people who actually believed in OOO. Pentium 4 was designed by people who really did not want to be doing OOO, but were forced to because the simulators showed what they really wanted to build did not work.

    Although Sandy Bridge was marketed as a P6 family core, it really is a step beyond."
     
  12. Gubbi

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    I think Glew is being overly harsh. P4 did have a *big* ROB with 128 entries. It was also the first Intel processor with a physical register file. The OOOe machinery of Sandy Bridge is a direct descendant of the P4. Every part of the P4 was a departure from the past. In hindsight, many of the choices were bad. The broken implementation of the RDRAM memory system, the trace cache based frontend with its over-reliance on getting branch prediction right, the speculative scheduling (ie. expecting loads to always hit D$) w. replay to clean up. Compounded by the problem that process tech ran into a brick wall with the end of frequency scaling and the start of massive leakage.

    Compare it to the Core architecture which was basically Pentium 3 optimized for power consumption. The lower power consumption allowed Core to become a success "by accident": Lower leakage operation, multiple cores and the shift from desktops to laptops were all in its favour.

    Cheers
     
  13. mczak

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    I think the execution core itself also had huge problems, not least due to the amount of different very specialized execution units, causing nothing but terrible latencies. Wicked fast adds but dead slow on just about anything else. Simple reg/reg shift? 6 cycles latency (ok improved on prescott at least). Coupled with things like the near-inability to read the flags register (for anything but branches, hence relatively simple instructions like setcc also have 5 cycles latency and this problem got much worse on prescott too, now setcc has 9 cycles latency, and of course my favorite cmovcc has 9 cycles latencies and throughput of one every 3 clocks whereas any old Athlon can do 3 per clock with a latency of one - ok that might be overkill) it is simply not a good design. Lots of interesting ideas, yes definitely but way too many drawbacks.
    And the simd unit is the most weird design ever, a simple reg-reg move executes in a special "mov" execution unit apparently and has 6 cycles latency (7 with prescott) ??? where the same chip can do int adds with 2 and float adds with 5 cycles latency? You gotta be kidding me. This design does not make sense (well to me, maybe someone can educate me there...).
    The whole chip looks like it was designed with "nice" code in mind (so essentially just simple arithmetic and well predictable branches), instead of code you'd see in practice.
     
  14. fellix

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    Every aspect of the NetBurst family was dedicated to serve the clock-rate mantra, that the steady and lean technology progress during the 90s provided. And it made a good marketing tool back in the day, as well. It was like a mini-dotcom bubble, until reality busted the door -- inevitable process limitations and the mobile boom.
     
  15. Gubbi

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    It was very much optimized for the common case, to the point where everything else was a pathological case.

    Cheers
     
  16. Raqia

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    There's some nice details about the unreleased, balloon payment mortgage iteration of netburst here:

    http://tweakers.net/reviews/740/chip-magicians-at-work-patching-at-45nm.html

    "Fisher has been on Intel's payroll for quite some time: he worked on the 486 cpu, the definition of mmx and sse instructions, and also on the Pentium III. The previous product that Fisher worked on was codenamed 'Tejas'. It was to be a 65nm version of the Pentium 4 with an extremely long pipeline of 40 to 50 steps, in order to achieve clock speeds of 7GHz or even higher.

    Work on Tejas had progressed considerably when it dawned on Intel, back in 2004, that there was no future for the Pentium 4 architecture. The team had just achieved the 'tape out'-point when news came in that the project had been canceled. The 'tape', which was meant to be sent to the factory to make the first physical version of the chip, is now lying in a safe gathering dust."

    Some eccentric billionaire should foot the bill to fab it and hire someone to do a full review of it. The wiki article has some nice tid bits too: http://en.wikipedia.org/wiki/Tejas_and_Jayhawk
     
  17. DSC

    DSC
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  18. DSC

    DSC
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  19. DSC

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    #559 DSC, May 12, 2014
    Last edited by a moderator: May 13, 2014
  20. pjbliverpool

    pjbliverpool B3D Scallywag
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    Sweet! That's the biggest CPU performance boost we've had for quite a while, should be a very nice chip.
     

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