Huddy says "R600"

For how long now have people been asking about this tech? My bet is that they're already using it. That, or they never will.

 

Why are unified pipes smaller than traditional ones?

 

Like I said, I'm thinking they'll be somewhat comparable to G71's pipes, so not just ALU's. I'm guessing similar to the ALU + (ALU or TEX) kind of shader pipe they've got going right now.

I'm thinking 32 if they go triple issue or 40-48 if they stay dual issue. They'll be a bit more simplified from the current setup, maybe taking 4 cycles for FP16/I16/I32 filtering (I'm crossing my fingers for high precision integer filtering), initial AF setup, cube map calcs, etc. Maybe they won't provide enough register space to hit that peak most of the time in order to stay compact.

I know that sounds like overkill, but again this ties into my theory that they'll leverage the current setup that they've perfected. With this design, I don't see them saving much space by reducing the texture rate, since the address calcs are done so fast, though I may be underestimating the ease of fetching data from the texture cache.

Of course, I could be way off, and NVidia could decouple the TMUs like ATI did. Then they'd sort of be abandoning their current architecture, though, as your gut feeling dictates. My gut feeling says they won't go that route until they decide to go unified.

 

I think SugarCoat was comparing to NVidia's pipes and pre-R5xx (with TMU logic). We already know that ATI added a lot of math power in R580 with only 60M transistors. This, of course, assumes they didn't take anything out of R520 that was "overbuilt".

 

I don't think more than 2-cycle latency on FP16 makes sense.

 

At first I was thinking the same thing, but when you do things on a quad by quad basis you can slow things down quite a bit while still saving space. I was just throwing ideas around, really. Xenos does FP16 filtering by converting to 16.16 and doing integer filtering at 1/4 rate, I assume by cascading the filtering logic (the filtering weights remain 8-bit or less). Some clamping could happen since FP16 range is more than 2^32, but it's a decent compromise IMO.

 

Why not? Considering that the most common case of texturing involves compressed textures and that G70 is completely bandwidth limited for 32bpt and above, I'd say it makes perfect sense.

 

Well, if you just consider that the G7x already is an extremely efficient piece of hardware in terms of die space, why should nVidia simplify things further?

 

IIRC it could only be used in a brand new architeture, so I would say it is R600 or never.

 

Why? It's just an ALU layout library.

 

Actually G80 is really Rampage 2 - but shhh! don't tell anyone

 

To be able to add more units.
Extremely efficient compared to what? It's not efficient to have units that can rarely sustain their peek processing rates. Maybe the additional cost was low. Maybe it wasn't, but c&p design was cheap.

 

Compared to their competitor.

 

edit: never mind

 

My gut feeling also says one step at a time

 

That transistor advantage might be moot when they slap GDDR4 on the R580.

 

I don't see what that would have to do with anything. It's just a memory interface like any other.

 

4 samples per pixel in a single cycle like Xenos. It seems like this feature is of more use in the PC than a console anyway.

 

Umh..are you sure? I think it makes more sense on Xenos (due to edram)