Huddy says "R600"

The burst length is increased from a minimum of 4 (as in GDDR3) to 8. This way, they can partition the internal organization into more parallel blocks and run the internal clock at half the speed of BL4. If the internal speed used to be the previous critical path in GDDR3, you suddenly have doubled the cycle time. The critical path probably now becomes the IO pins.
Since your minimum transaction packet suddenly doubles in size when going from BL4 to BL8, you'll have to work hard to keep rams busy at high efficiency. That requires (more) complex scheduling and large cache sizes.

 

Thanks, now it makes sense!

 

BTW, the R580+ article that Uttar pointed to doesn't make a lot of sense:

If you really bend your head around it, you could maybe discover that it's trying to say that the burst size increased from 4 to 8, but it's far more likely that the writer didn't understand what he was talking about. How do you 'double the number of bits on an IO pin' ??? Only by going from double to quad data rate. Which is definitely not the case for GDDR4.

The explanation about latency increase is also very questionable. There's no reason why GDDR4 should have more random access patterns and I don't see how changes in addressing (assuming they are at all there) impact latency.
It's the BL4 -> BL8 that's doing all the evil.

Edit: small correction: addressing latency will go up by 1 cycle, but, again, that impact is minor compared to the BL increase.

 

Basicly we can get from RGBA8 to FP64 for free!! j/k

 

When you think about it, it must be quite scary (for a chip architect): your minimal memory transaction is 32 pins * 2 (DDR) * 8 (BL) = 512 bits or 64 bytes. If you organize your memory controller as 64-bit controllers, your minimal transaction is 128 bytes. (I think that ATI doesn't do the latter.)

Say you need to change only 1 byte in such a 128 byte block, that gives you a BW efficiency of less than 1% ! So you better find ways to groups transactions as much as possible... which increases cache size and increases latency... which increases internal buffering requirements even more.

It gets worse when you need to switch from read to write and back or switch from one row to another: there are a lot of different timing contraints that much be met and they all reduce performance.

I'm happy I don't have to deal with that in my job.

 

Well..it gives them a lot of good reasons to give us more-samples-per-pixel-anti-aliasing(tm)

 

Burst length is not given in clocks but bits AFAIK, so it's only half that.

 

Yes, you're right. I should have looked that up first... BTW, the datasheet can be found here.

 

So in the end at this point in time with GDDR3 and GDDR4 in the coming generations, is it really worth the extra cost for GDDR4 now? I know that both cards manufacturers keep things close to the chest but hmmmm. I know ATI put alot of effort in its memory controller in the R580? ( If memory serves me correct.) Im just wondering if ATI might have some new sytems when dealing with memory BW and latencies and make the most of the burst increase to 8 that comes in the GDDR4.

Another thought or question actually. Does anyone see XDR memory coming into play at some point? I know right now its not cost effective but just a thought? We all hear you can never have enough BW and CPU's are often considered the bottlenecks. Now that Dual and Quad cores are coming maybe we will see XDR in the R600 or G80 or close relatives?

 

GDDR3 is really GDDR2, they just tweeked some of the signalling. GDDR4 ~= DDR3. In botth GDDR4 and DDR3 the memory devices operate in a prefetch of 8 mode internally, while GDDR2/3 and DDR2 operate in a prefetch of 4 internally. So a part that bins to say 450 Mhz GDDR2/3 will run at a pin rate of 1800 MT/s while a GDDR4 device at the same bin frequency would run at 3600 MT/s.

Aaron spink
speaking for myself inc.

 

R600 have 8 MC channels (A/B/C/D/E/F/G/H) compared to R580 have merely 4 channels of that (A/B/C/D)

maybe someone know what I adumbrated . and dont spell out........................

 

nope ,R600 would be either 32bitX8 or 64 bit X8 MC capable ASIC.

 

R580 has 8 memory channels (4 primary ring stops with two channels per stop).

 

GDDR4 requires less pins.

Jawed

 

It puzzled me why it wasn't 8 ring stops. I surmised that it boiled down to there being 4 PS pipelines (screen-space tiling).

Makes me wonder whether R600 could go as far as being 8 ring stops therefore 8 pipeline, 32-1-3-1... Each ring stop would have a 32-bit channel to two 512Mbit chips for a total of 1GB.

But ATI makes noises about going higher than 3:1 ALU:TEX, so it seems doubtful it would be 32-1-3-1. Unless that's being saved for the refresh: 32-1-4-1...

Jawed

 

Is the first number the amount of "ROPs" hypothetically?

 

hmm if ATi goes 512 are the expecting that there will be no other bottlenecks to achieve peak performance on the r600? I would think the r600 will need 3 times more the shader, fillrate performance of the r580 before that happens, if it really is 512 bit. Thats alot of complexity and cost to add for something that might be bottlenecked in other areas.

 

Wouldn't 8 stops just mean a higher latency because the max number of hops is 4 instead of 2 in the current one? I guess if the chip is a lot bigger then they could make it 8 stops.