how is xenon's edram's bandwidth calculated?

Discussion in 'Console Technology' started by shuipi, Feb 28, 2007.

  1. shuipi

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    "Its design allows for free multisample antialiasing (MSAA) while maintaining a sustained rate of reading or writing 8 pixels per GPU clock cycle—256 GB/sec of memory bandwidth."
     
  2. Zeross

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    I think it's something like this :
    8 pixels / cycle x 8 bytes / pixel (color + Z) x 4 (multisampling) x 2 (read-modify-write for blending) * 0.5GHz = 256 GBytes/s
     
  3. shuipi

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    but it said read OR write
     
  4. TurnDragoZeroV2G

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    It's exactly enough bandwidth required to do those operations. If you're only writing, you can only use (and only need) half of that bandwidth. Everything is based off 8 pixels/zixels per clock. There's the bandwidth to read AND write 4 samples for 8 pixels per clock.

    So I'm not certain what you're really asking.
     
  5. Zeross

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    In the case where you're not using alpha blending you can't use more than 192GB/s this is the worst case scenario (back-to-front rendering : reading AND writing a Z value for every fragments).
     
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