Help me understand something about node speed gain and power reduction

[johndoe]

For example, TSMC's 10nm process will have "2.1 times the logic density of the 16nm node along with a 20% speed gain and 40% power reduction".

I understand that based on the density figure, you could resize a 16nm 600mm^2 processor die to take up only 47.6% of the same space on 10nm (286mm^2). And, presumably, have it run either 20% faster or reduce its TDP by 40% (you can't have both)?

But what would happen to the speed and power figures if you were to make the 10nm die 600 mm^2, the same size as the 16nm die? It would of course have 2.1x as many transistors, but could it still go 20% faster or have 40% less power? Doesn't adding transistors increase the power consumption?

TL;DR: Basically, what I'm asking is this: Do the improved speed gain and power reduction figures between nodes only apply when the processor is literally shrank, meaning it has the same number transistors?

 

[Alexko]

For example, TSMC's 10nm process will have "2.1 times the logic density of the 16nm node along with a 20% speed gain and 40% power reduction".

I understand that based on the density figure, you could resize a 16nm 600mm^2 processor die to take up only 47.6% of the same space on 10nm (286mm^2). And, presumably, have it run either 20% faster or reduce its TDP by 40% (you can't have both)?

But what would happen to the speed and power figures if you were to make the 10nm die 600 mm^2, the same size as the 16nm die? It would of course have 2.1x as many transistors, but could it still go 20% faster or have 40% less power? Doesn't adding transistors increase the power consumption?

TL;DR: Basically, what I'm asking is this: Do the improved speed gain and power reduction figures between nodes only apply when the processor is literally shrank, meaning it has the same number transistors?

Yes. If you doubled the transistor count and kept the speed constant, you'd get (100%-40%)×2 = 120% of the original power consumption. And yes, "20% speed gain and 40% power reduction" is marketing speak where "and" really means "or". If you wanted to double everything while keeping clock speed and power consumption constant, you'd have to make micro-architectural improvements as well.

And technically, you couldn't really shrink a 600mm² die to 286mm² or even 300mm² because a good chunk of it would be I/O, not logic. And I/O doesn't scale very well.

 

[johndoe]

Okay, thanks! Very helpful.

One more question: If I'm understanding correctly, you could get a 20% speed gain if you didn't reduce power consumption. If you then doubled your transistor count, would power consumption double while the 20% speed gain remained?

 

[Alexko]

Yes, that's right. Of course these are just rough figures given by TSMC, and reality may be more complicated, but that's the idea.