Enhanced Cell B.E. for HPC at Cool Chips X

If those structures were included in the 90 nm transistor count, I don´t see any reasons either.
I am just grasping at straws to find some kind of logic behind the size numbers.

 

A serial memory interface needs much less pins than a parallel one, for one thing. It's even on one of the slides. Pin areas are huge, relatively.

Edit: driving them also increases the power requirements significantly.

 

The Opteron memory controller produces less than 10 watts.
Even doubling the bandwidth with double the controllers won't make up the possible 40+ watts in savings that would have resulted from a decent process shrink

 

Agreed. But 65 nm is especially bad for leakage. Even Intel had the same problem.

 

Thanks for the article!

glad to see them get the much wanted DP FLOPS

and a big improvement on RAM size!

 

The new DP units explain most of that.
They add what looks like about 1 mm to the top and bottom sides of the chip, that's something in the region of 20sq mm - half of which appears to be wasted. Add more for 4 memory controllers and zillions of pins and you have a substantial amount to add on.

I can't explain the power so well but you'll probably find some of those transistors are big power transistors, not normal logic.

My understanding is that is a quick upgrade, done to get the chip out the door as fast as possible. Thus a lot of the space and power optimisation that could be done hasn't happened. If they do a DD2 it could be quite a bit smaller and quicker. However they may just go direct to the 32 SPE version in 45nm.

 

Well, out of the total 100 watts, the memory controller(s) probably does explain at least a material percentage of it. After all it's more than increased addressability they were going for, but similar bandwidth levels as well; on DDR2, that's going to require a lot more relative to the XDR variant of the chip.

The wire tracing on the motherboard is going to be ugly, that's for sure.

 

Not at all.

Yes, I appreciate that. But from the figures we've got, I'm inferring the normal Cell's performance.

They've added 9 million transistors, and reduced the die size (not package) by 23 mm^2. Thus if they lost the 9 million extra transistors, die size would shrink from 235 mm^2 to 204 mm^2, all things being equal. Has the addition of DP prevented the expected reduction, and we can still look forwards to 150 mm^2 65nm CBE? Or is the degree of shrinkage demonstrated here going to apply to PS3 Cells? A 15% reduction is very poor for the switch. I don't know enough about chip manufacturing to know why, with transistors half the size as 90nm, the die can't be shrunk as much.

 

They probably didn't do a full shrink because they didn't see the need to, or because this is still an early revision that needs to undergoes several more revision. Or they need the area to fit all the pin they need to have 25 GB/s of bandwidth using DDR2.

But in regard to power, it seems to be inline with the other chips being compared too. Probably leakage and such is problematic. And the fact its 3.2 GHz doesn't help.

 

Transistors are not the things which take up space, wires are far bigger and don't shrink at the same rate (if at all). This version will have a whole load more wires with all the extra pins.

 

Duh. Bandwidth is expensive, computation is cheap ... where has he been?

 

That's not saying much.
A single SPE in a lab can be made to do a lot of things a full CELL processor cannot.

The voltage needed and the power draw would be too high to make it meaningful for Cell.

 

It's saying something though. The original SPE's could, in the lab, get to 5 GHz at not too stupid voltages. That was downclocked to 3.2 GHz in the wild. An ability to attain 7 GHz best performance would imply >4 GHz attainable real-world. And referring to that .ppt, 5 GHz was achieved at 1.0 volts. That compares with the 3.2 GHz at 0.9v of the 90nm part, the limit in the CBE. So 7 GHz chips in your workstation? Nope. But 5 GHz? Possibly...

 

The package must also be really huge. I wonder if they were so pad limited because of that DDR2 controller that they needed to put some dead space in the layout to make room. It's been done before, but people usually go through revisions to improve the layout. That could theoretically account for some die space issues, as could routing signals through the chip (assuming they had to make changes here to account for the wider bus), which could have been saved by adding more interconnect layers. In any case, I'm grasping at straws myself because both power and die size had little improvement at this shrink.

As much as an XDR controller is low power compared to DDR2, I can't see that alone accounting for a lot. Leakage increase is a definite possibility (especially since it's on a strained SOI process (?) -- someone else may be better suited to comment on this), and I'm guessing this was probably a bit rushed because they may have a lot of potential customers eyeing Cell whose appetites they wanted to whet ASAP. Normally, I'd expect IBM of all companies to do better. Sure, these may be TDPs rather than a true power consumption, but you'd still expect that to go down a good amount with a process switch.

Well, we can only hope that a PS3 counterpart will surely have more work done to it to bring power down, as the absence of a single working SPE will hardly account for more than a few watts. Late in the development of the PS3 Cell, we were hearing all these things about Sony and Transmeta doing some work on power-saving techniques, and it was too late for the initial PS3 Cell production lines, but maybe not for 65nm. I honestly don't know what they could do or what they're not yet doing, but it would take some serious complacency to do much worse than the current state suggests.

 

I'd like to see a schmoo plot for the 65nm variant.

Process transitions lately have been hit or miss, and I don't want to assume anything when it comes to extrapolating from the previous process node.

The assumed linear progression that worked above 90nm does not automatically apply to what goes on below.

IBM's slow 65nm process transition and the lackluster performance of 65nm for its tech partner AMD makes me think the scaling to 5 GHz within Cell's current thermal envelope is going to be difficult.

 

This doesn't belong in consoles, clearly.

Not sure why Cell is consistently allowed to slide in that area.

 

^^^ what he said.

 

I didn't know PS4 was not a console. So, does it make coffee instead, at least?