dual (or more) channel memory in graphics?

Thanks! Heh, I meant to say the data lines were multiplexed at the controller between the cores, not a multiplexed bus (which from my undergrad days implies some sort of time-sharing between different devices on one physical bus with a multiplexer at one end and a demultiplexer on the other and synchronized control signals).

I've never heard this before but it makes sense. Assuming the address request lines aren't encoding two bits per cycle this really is the only way DDR could possibly work. What's misleading is that a device with 400Mhz DDR SDRAM running on a 128bit bus is refered to as "800Mhz effective" rather than the more accurate "256bit bus effective."

 

Both "800MHz effective" and "256bit bus effective" are equally (in-)accurate. You do have an 800 Mbps data rate, or if you only look at the memory clock (400MHz) you do effectively get 256-bits/clock.
The description "128-bit, 400MHz DDR" accurately tells you everything. The clock rate is 400 MHz, and address&command is transferred at that rate. The data bus is 128-bits wide and it is a Double Data Rate bus, meaning it transfers data on the positive and negative edges of the clock, so you get 800 Mbps per data bit. It's pretty clear.
The problem is that the PR/marketing people wanted to shout larger numbers, so they decided to call it 800MHz.