dreamcast development board...

Discussion in 'Console Industry' started by sinektik, Aug 25, 2010.

  1. sinektik

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    anyone know what the config was for this dreamcast set4 board...it has 2 powervr-like chips, i have heard that early on the tile accelerator was a seperate chip...

    [​IMG]
     
  2. Simon F

    Simon F Tea maker
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    That's probably a Naomi 2 with an Elan T&L chip driving a pair of CLX2s. It's been a long time since I last saw one. Do you have a link to a better picture?

    [UPDATE] On second thoughts, 1997 is probably(?) too early for Elan. I wonder if it is an ARC1which was the predecessor to CLX. Again, I'd need a better view of the board.
     
  3. sinektik

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    that's what i thought about it being a naomi 2 derivative as well...

    i first saw photos of this board 4-5 years ago and since then all we know about it is that it was an early dreamcast set 4.25 devboard paired with a rev. C cross products debug adapter and a gd-rom emulator (not pictured here) made in 1998. Finalized dev hardware is set 5.24. I hypothesized that not all clx2 functions had yet been integrated on a single chip or that sega was experimenting with dual pvr solutions as early as 1997...Anyway, the dating of dc's dev hardware is a bit confusing, they had this board ready in 1997 and the first piece of kit that was massively available to studios was a clx2 pci card with the kamui api on April 1998...

    I know a guy who has one, i will try to reach him and get a better picture of the whole setup.
     
  4. sinektik

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    ...

    i managed to find the sdk that was meant for use with this board. The kamui documentation states that as of that stage the following platforms were supported from the library:

    a) PC IRIS + ARC1 evaluation board
    b) SH4 COSMOS + ARC1 evaluation board
    c) SH4 HOLLY (CLX1)

    So i think it is either b) or c) as the main cpu on board looks identical to an sh4. In other places the documentation states it supports an ARC1 + a tile accelerator. Also the same document states that Holly is capable of bump mapping, trilinear filtering and modifier volumes whereas ARC1 is not. Later i also found in the readme file of the SDK that features such as bump mapping and trilinear filtering are not supported on the set4, so i think everything points to an ARC1+tile accelerator...

    more later when new pics are available...
     
  5. Simon F

    Simon F Tea maker
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    FWIW ARC1 was a PC chip (i.e. PCI bus) so if there is an SH4 on that board, then the 3rd chip will, most likely, be an interface between an SH4 and PCI. It's been a very long time so I don't remember the details of what was in ARC1 but I think it had much of the functionality of CLX* but perhaps missed some "extras" such as 4 and 8bpp palette textures. There were other implementation improvements such as the VQ texture decompression hardware being more efficient and I think the clock frequency went up significantly.
     

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