DDR3 Cycles latency

Discussion in 'Graphics and Semiconductor Industry' started by pMax, Jul 2, 2013.

  1. pMax

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    Does anybody remember the average latency needed to make a full access from RAM by current gen CPUs (L1+L2+L3+DT)?

    If my memory holds true, it was around 150-200 cycles.
     
  2. itsmydamnation

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    who's cycles, CPU core, memory control, the memory itself?

    also wouldn't all memory access be via L1+l2+l3, ie you have to check if its there before jumping to memory.
     
  3. fellix

    fellix Hey, You!
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    That's highly dependent measure. A quad-channel stock LGA2011 processor can hit ~250 cycles in wait time for the requested data, if the HW prefetching doesn't interfere. All modern CPU architectures are quite a lot latency tolerant, depending on the load type. Benchmarking alone doesn't tell the full story and usually shows either the worst or the best case scenario.
     
  4. pMax

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    Hi,

    yes, I was referring to CPU clock cycles. Was thinking of the 'worst case', where you miss Lx, and your request has to go to the memory controller ->dram controller->preload etc.
     
  5. brunogm

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  6. jaybraueir

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    The DDR3 2000 CAS9 will take 9/2000 seconds, which is equal to 0,0045 seconds, to respond while the DDR3 1600 CAS 6 will take 6/1600, which is equal to 0,0038 seconds, to respond. Thus, the 1600 one is faster.

    Less RAM sticks generally means less load to the memory controller. So, 2x4GB is better than 4x2GB.
     
  7. aaronspink

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    You are using the wrong numbers. The common terminology for DDR3 uses the data signaling rate which is 2x the cycle rate of the device. A DDR3 2000 part is running at 1 GHz command rate and therefore a DDR3 2000 CAS 9 part will have a CAS latency of 9 ns. Likewise, max CAS rate will be 1 CAS at most every 4 command cycles as well. Internally the DRAM for a DDR3 2000 part is running at 250 Mhz.

    A DDR3 1600 CAS 6 part will take 6x1.25ns from CAS to data or 7.5ns and will be running at an internal frequency of 200 Mhz.

    As far as configuration of DIMMs and banks it is heavily dependent on the workload being used. For light and regular workloads 2x4GB might be better, but for most other workloads you want as many banks/ranks as possible to maintain maximum bandwidth since you are generally per bank command rate limited.
     
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