ATI Talks R5xx

Discussion in 'Beyond3D News' started by Dave Baumann, Nov 1, 2004.

  1. AlphaWolf

    AlphaWolf Specious Misanthrope
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    The best info I have suggests around $2 million for a 90nm mask set.

    If you have any factual information to show otherwise, feel free to link it.

    <edit> sorry forgot to add my link

    http://www.eetimes.com/semi/news/OEG20020617S0050

    I realize its old info, but I haven't found any newer.
     
  2. atomt

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    Wafer cost

    $1047 is the Average Selling Price of a TSMC wafer. This have gone thru the works except for wafer sort (functional test done on wafer)

    $20K could not possibly be correct even in 1999 and 0.25um process.
    Athlon (K7) was introduced in 0.25um/Al process using Fab 25 (Austin), on 200mm wafers.

    Die size of Athlon = 184mm2.

    200mm area = pi r^^2 = 31,416mm2.

    # of die per wafer = 170
    (Actual probably closer to 160 due incomplete chip on the edges and test die)

    Yields were low for such a large die on a leading edge process. (K7 was available only in limited quantities until Fab 30 - Dresden comes online with 0.18um Cu process)

    My GUESS on Athon yields is ~15% due to large die size.
    If wafer cost $20K, Athlon would have cost $833 even b4 packaging/BI/test

    -----------------

    A more recent comparsion.

    Sempron is 84mm2 (die size did not drop that much because of added L2 cache) It is on 200mm/0.13u.

    Dies per wafer = 374 (actual ~ 360)

    Yields probably ~ 45%.

    At $20K/wafer, it will be $123. Add to that assembly, burn-in, test, ..
    Low end sempron is available for $50.
     
  3. Anonymous

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    Re: Wafer cost

    I'm not trying to dispute you -- based on your posts you are certainly more knowledgable about the customer/foundry signoff/handoff process than I. But the price-delta may be due to the foundry's relationship with the customer.

    TSMC and UMC's aggressive pricing is due to their practice of selling "bare wafers" (full processed, uncut, untested.) This on one of end of the spectrum, where "customer is expert.' I.e., customer must deliver a 'mask-ready' GDSII database to the foundry, who offers no design assistance. Other merchant foundries, especially IDMs like TI, Fujitsu, Toshiba, IBM, LSI, etc. generally do NOT deliver bare-wafers, but base contract-pricing on KGD (known good dice.) They may also offload *some* design-activities (place&route, and everything after that), reducing the customer's tapeout responsibilities. Finally, I think the highest level of customer service are "turn-key" foundries -- they'll practically handhold a customer through the design's front-end synthesis all the way to tape-out.

    Anyway, depending on the level of service provided, a IDM/turn-key foundry will charge anywhere from 2X-5X more than TSMC, per "equivalent" wafer (equal quantity of usable dice.)

    For small fabless companies, or projects with low projected volume, an IDM or turn-key service is attractive. The foundry is handing a great deal of work that would otherwise require extensive investment (in manpower and tool-infrastructure) on the part of the customer : paying a premium per wafer is justified.

    For example, one of my company's customers wanted to switch from a IDM-foundry to TSMC, because the IDM was charging them the equivalent of $300/die (90mm^2 0.18u standard cell.) My boss calculated that the same design would cost $50/die if re-targeted for TSMC. But it wasn't practical, because the customer used a lot of the IDM's IP (design lock-in), and the IDM also handled the substrate-design for the BGA-packaging. (TSMC doesn't do any packaging for you -- and at the time, an ARM9-license started at ~$500k USD.)

    I know I read somewhere that NVidia's NV30 was a "special-case", in that NVidia paid TSMC per 'known good die.' That's rare for TSMC, and it's unlikley TSMC will ever want to do something like that again.

    *IDM = integrated device manufacturer (semiconductor company that sells finished chip-products and manufacturing capacity.)
     
  4. Bouncing Zabaglione Bros.

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    Nvidia effectively gave up a lot of profits in order to deliver SM3.0 at .13. They sacrificed profit in order to gain DX9 market share, which was not something ATI were willing to do (or really needed to do with their R3x0 dominance of that market).
     
  5. Anonymous

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    The NV30 was produced by IBM, and that is why they paid for good die's only, I don't think you could do that with TSMC
     
  6. Dave Baumann

    Dave Baumann Gamerscore Wh...
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    NV30/35 was TSMC 130nm, the only NV3x to be done at IBM was NV36 and then NV40 after that.
     
  7. _xxx_

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    ATI will pay as much as they have to, since they want to release a new product at some point in time. They'll do pretty much whatever it takes, just like any other company would.
     
  8. JoshMST

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    I thought that only initial test wafers and whatnot were paid in full by the companies ordering them, but when full production starts up they typically pay on a "per good die" deal. This is what Mike Hara of NV told me, so there! I actually put a name to "one of my sources"!

    If that was the case with IBM, then NV probably paid a pretty high price for each good die, but they probably paid a lot less than if they had gone in "per wafer". In the usual cases though, the amount paid is probably a wash, but this protects companies like NV and ATI if yields are thrown out of whack during the middle of a run, or something like an earthquake happens and hundreds of wafers are ruined.
     
  9. 2senile

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    Could you elaborate a bit for a "noob"? I've had "info" in the past from employees of companies that weren't qualified to give the info'. Damned marketing Dept!

    Is Mike Hara in a position to positively state that?

    Please understand that I'm only asking for confirmation as everything I've read in Forums suggested that the "per good die" was unusual.
     
  10. JoshMST

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    Mike Hara is VP of Investor Relations at NVIDIA. As such he has pretty good knowledge of how NV is dealing with the foundries. He told me quite succinctly that NV worked with TSMC on a "per good die" basis. Now, whether that has changed from when I last talked to him, I couldn't say.
     
  11. digitalwanderer

    digitalwanderer Dangerously Mirthful
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    When about did he tell you that? (Just a rough idea please, like this year or last year)
     
  12. atomt

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    Wafer Cost

    The info was from www.digitimes.com comment on UMC/TSMC 3Q financial report. Not subscriber, so cannot access archive. So either memory failed me or digitimes misquoted $1047 ASP.

    From TSMC financial release (available from most financial sites, Yahoo, WSJ)
    http://tools.thestreet.com/tsc/quot...;symb=tsm&sid=44543&orig=1&timer=

    Exchange rate : US$1 = NT$33.47
    Revenue = NT$69.74
    8" equivalent wafers ship = 1333K

    Average revenue per wafer = NT$52318 (US$1563)

    TSMC also provides the following optional services :
    TSMC is one of 6 major chipmakers with internal mask shops (Intel, IBM, TSMC, NEC, Micron, Samsung) Top mask maker shops are Dai Nippon Printing, Phototronics, Dupont Photomask, and Toppan Printing Co.

    Wafer sort. - The bigger companies tend to bring it back for in-house sort or go to another contractor such as ASE/SPIL/Amkor.

    I no longer deal directly with foundry, so current info are from sources. A few years ago, we were evaluating a leading edge TSMC with internal fabs and the price are pretty comparable. We considered foundry because our division was the not the A-team (the big profit generator) in the company, so we could not get access to a leading edge process required to meet performance targets.
     
  13. atomt

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    Known Good Die

    I heard Mike Hara said that in a investor presentation. (I listened the webcast) It was last year, not long after the NV30 fiasco.

    To say that Nvidia management LIES may be a bit strong. Nvidia is known for misleading or distortion of truth.

    Wafer yields depend on fabrication yields (process issues) and design marginality, redundacy, etc. 2 designs can be manufactured, but a marginal design can receive horrible yields on the same process. RV410 and R350 both have similar transistor count. (120M vs 107M) If ATI try to manufacture RV410 in 0.15um process, yields could be disastrous because 0.15um may not be adequate for PCI-E interface 2.5Gb/s signalling. Not to mention other design marginalities caused by layout. ATI did not have a problem with TSMC low-k but Nvidia could not get it to work.

    So for high volume mature process (>= 0.15um) where the yields are stable, it is usually by wafer for simplicity.

    For full service whereby the vendor is responsible for test program, packaging, etc, KGD pricing is OK.

    For a new process, yields could be horrible. So it is really up to the two parties to work out some kind of mutually agreeable formula.

    When foundry business is bad, and a tier 1 customer could negotiate for a more favourable formula.
     
  14. Anonymous

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    Im just wondering wouldnt Fast 14 technology have some impact on overall transistor count, cost, heat, etc? I have read many of the benefits this technology could have for ATI and now seems like the perfect time (next gen GPU, embedded ram) to put it to good use :D

    Could this be the "underrated" technology ATI has up its sleeve?

    Till now I never heard or seen uses of the Fast 14 tech but if it even delivers half of what has been written, it would really give ATI an added edge :twisted:

    Anyone agree or disagree with this? If so why?
     
  15. Karma Police

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    All that has been said about The R5x0 is that it is on TSMC's 90nm process. But doesn't TSMC also have low-k 90nm process? Wouldn't the R5x0 be on a low-k 90nm process & not a normal 90nm architecture?
     
  16. Wunderchu

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    AFAIK, it is assumed that any 90nm process at TSMC at the moment, will be low-k...........


    DaveBaumann posted in this thread: ( http://www.beyond3d.com/forum/viewtopic.php?t=11986&postdays=0&postorder=asc&start=0 ) back in April,
     
  17. aaronspink

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    No one has been able to get a spin back in 2 weeks for years. With the number of process steps for both the mask set and the wafers, you are doing extremely good to get a 6 week turn around. And contrary to general belief, pricing isn't generally for wafers but for boats of wafers.

    Standard turnaround for a foundry is generally in the 3-4 month range from tape-out to packaged parts.

    And the cost of a rocket lot is minimal compared to the cost of the mask set for the spin.

    Aaron Spink
    speaking for myself inc.
     
  18. aaronspink

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    Doubtfull.

    Aaron Spink
    speaking for myself inc.
     
  19. Anonymous

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    Just a correction, R100 and up. Besides the Maxx "flaw", all radeons can be considered multi chip capable.
    R100 Dual chip

    [​IMG]

    R200 Quad chip

    [​IMG]

    From
    http://www.ati-news.de/cgi-bin/News/archives.cgi?category=1&view=7-02
     
  20. digitalwanderer

    digitalwanderer Dangerously Mirthful
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    What kind of sockets do those cards go in?
     
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