ATI Talks R5xx

Discussion in 'Beyond3D News' started by Dave Baumann, Nov 1, 2004.

  1. Dave Baumann

    Dave Baumann Gamerscore Wh...
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    No, you're not the only one - site stats bear this out!!

    That might not be the case as it looks like TSMC is eager for some 90nm demand.
     
  2. AlphaWolf

    AlphaWolf Specious Misanthrope
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    You might call the $2 million it costs for a 90nm mask many millions, I find it easier just to use 2.
     
  3. JoshMST

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    Haha, are you positive that a set of masks costs $2 million? I was throwing out some numbers, but these things are damn expensive. Even in the article that Dave pointed out to, it clearly says in there:
    I am sure if you discount one or two million here and there that you would make a fantastic CFO of a corporation... :p
     
  4. Leto

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    What does wafer and mask mean?
     
  5. atomt

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    Mask cost

    A mask cost from $25 to $75K. The more ML u have the more mask is required. It is definitely over a $1M.

    Fabs process wafers by the boats (carrier). For 300mm, 25 wafers per boat is loaded into furnace. Ordering 1 wafer is not going to save very much since the cost is in the processing and not the silicon wafers.

    It takes 13-16 weeks to process the wafers for 130nm. It depends on the number of process steps. (more metal layers, more steps) For engineering lots, it is common to ask for "hot" status (priority) That is the engineering lot get loaded into the next process step first.

    I don't know whether TSMC does "rocket" status for customers. Rocket status means that the equipment for next process step is kept idle, so that when the wafers finish processing the current step, it can be loaded in the next equipment w/o any delay. A lot of wasted idle time for expensive equipment and normal production is disrupted. At my x-company, Senior-VP approval is required for an engineering lot to get "rocket" status. Even rocket would "probably" still take 6-8 weeks at 90nm. Cost $$$$$.

    Designers normally put spare gates all over the layout. So minor changes
    can be done at the top metal layers instead of all layer relayout. Save layout time, mask cost. For high priority projects with $$$ budget, a standby lot is processed all the way thru until the just b4 top ML. So if the fix can be done in top ML, wafers could be available in a couple of weeks.
    If desgn require an all-layer fix, the standby wafers are coasters.

    Due to this cost and long turn-around, a lot of effort is put into verification. For fixes, it is FIB milled for verification b4 commiting to mask.
     
  6. atomt

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    Wafer cost

    TSMC ASP per wafer last quarter is $1047. (30% of TSMC is 0.13nm and below and most fabs are 200mm with a couple at 300mm)

    I don't know exact cost of 200mm 130nm wafers (processed) but I have seen it quoted at between $1500 and $2000 and $3500-$4000 for a 300mm wafer.
     
  7. JoshMST

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    I am assuming that is the cost of the raw wafer with no litho or anything done on it? I ask this because I was told by a CTO some years back that a fully processed wafer could cost as much as $20K (and this was 5 years ago at 250 nm).
     
  8. Anonymous

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    ~R500 ~550Mhz VPU 1 TMU 32 Pipes PC version (2 TMU 16 Pipes each XBOX version)
    ~260 mil transistor 0.11 low k!!!!
    ~700MHZ (1400MHZ effective) GDDR3 - 256bit bus ----> r600 512bit bus
    8 VS Units. GPU itself is going to have internal cache memory only PC version!
    SM3.0 support, DM support, VS3.0 support, OpenGL 2.0+


    This is real info!!!!

    I will remind you on this by the lunch time next year... :wink:
     
  9. karlotta

    karlotta pifft
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    Well i will just say yur wrong now and save the bandwidth next year. There is no Low-K .11. The R500 and R520 are diff chips. Also ATI will not be producing the R500, MS will. As for trany count, well under 300 (240). This will be a OEM part too.
     
  10. Anonymous

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    the Xbox 2 version will certainly blow through the 300M transistor mark because of eDRAM. at least 10 MB worth if not more.
     
  11. Richard

    Richard Mord's imaginary friend
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    I just wonder what made them change from low-end try out new processes to test the waters, high end follows. Perhaps they are expecting even more shortages next year and decided the low-volume/high margin chips is a better solution?

    I agree and AFAIK AMD's use of 90nm process has not demonstrated the same problems. What I am wondering is if the R5xx will follow in the NV40's footsteps of double-slot/monster cooling.
     
  12. loekf2

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    Cough... cough.. I was more thinking of a million dollars for just a tapeout...

    (anybody any clue how many respins/metal fixes companies like ATI or Nvidia do ? I have the impression that they try to fix a lot using emulation, like Quickturn)
     
  13. 5150 Joker

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    Dave or anyone else--

    What are the chances of an SLI-like feature being implemented into R520?
     
  14. loekf2

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    In simple terms:

    wafer = thin slices of silicon, on which ICs are manufactured using advanced lithography
    mask = basically the negative of an IC (like a photo). The manufacturing process consists of several steps, where the layers are added using lithography (using light). A mask is a plate of glass, on which the geometry (structures) of one step are put. Using light sensitive resist (correct word ?) you can put a structure on the silicon. Then fill the gaps etc. I guess you get the picture.
     
  15. loekf2

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    In other news (see Xbitlabs)....

    Someone from ATI already stated that multi-GPU support has already been in the R3xx/R4xx from the beginning. Maybe they are considering more GPUs per card instead of connecting two GPUs via some kludge. If you ask the bandwidth of a single PCIX lane should be enough to feed two GPUs or am I doing the wrong math here ?

    There're also stories that SLI-like support or multi-GPU support could be something for ATI-only chipsets/motherboards.
     
  16. loekf2

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    Maybe off-topic, but did I see somewhere in San Jose a few weeks back some ad for a company who claims to have invented embedded SRAM with an even higher density than 1T SRAM ?
     
  17. Dave Baumann

    Dave Baumann Gamerscore Wh...
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    Partly they may have been bouyed by their transisition to Low-k, which will be important for 90nm. However, probably a fair element of necessity in this instance. As the Orton interview states they thought they would need it for their architecture and 90nm wasn't ready for 2004 - in order to get SM3.0 in the market as soon as possible they needed to adopt 90nm ASAP. We also don't know which parts have taped out first and what the arrangement with MS was - I'd imagine that MS's stipulation was to use 90nm for Xenon and the work on that may have benetitted R520 or vice versa.

    The comments indicate that the die will be smaller, so this would suggest the opposite in fact - but then they may opt to shoot for a massive clock which might make it necessary.

    You tyr and get a lot during emulation, but inevitably things turn up when you actually put them into silicon that you don't forsee. Semi's will try and do them in as few spins as possible, but two is quite comment - a few more if its the first of a new architecture (R300 was A13, which means it had 3 minor revisions, RV380 released at A22 which I think means it had one major metal revision and possibly and respin as well).

    R300 and up has had inbuilt hardware for multi chip operation from the off - they are used by E&S and SGI rendering systems as such. For them to bring multiboard to market is more of a software and business issue.
     
  18. Tim Murray

    Tim Murray the Windom Earle of mobile SOCs
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    WRT to multiple cores on a single card--are the days of Voodoo5-style multiple-core-per-board cards definitely over? Considering both IHVs are disabling quads to get upper-mid-end boards, is it possible to replace the quad unit on a chip with a core? Seems to me that it could be more cost-effective to output a load of low-end cores that were cheap and had near-perfect yields to create your lineup rather than do that from the top down and produce 3 separate cores to make five different cards.
     
  19. Richard

    Richard Mord's imaginary friend
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    Right... hmm... so, would it be fair to say they are more concerned about wields than performance?

    Indeed. I was very surprised to read about the tranny budget for 32-bit precision alone. You argument of necessity fits like a glove. However, nVidia doesn't seem to be too bad with its 130nm with horrible "wafer per die" results and now the rumoured NV41 to recoup losses.

    I think it's interesting both vendors are taking different routes (at least so far --- any news on what NV has in store for the NV50? Or perhaps it will just go for a speedbump NV48 on 110nm?).
     
  20. Dave Baumann

    Dave Baumann Gamerscore Wh...
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    Thats because NVIDIA's architecture isn't ATI's. NVIDIA chose to implement it in a fashion they did, but that doesn't mean that ATI will do something the same. If you remember back to Richard Huddy's notes in the leaked presentation you may recall the comments on branching performance - perhaps ATI feels that this is the real significant element of SM3.0 and feel that to address it properly they need more transistors in this area; there could be plenty of other areas of consideration such as that.
     
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