ATI RV740 GPU and Architecture analysis

Discussion in 'Beyond3D Articles' started by B3D News, Sep 26, 2009.

  1. B3D News

    B3D News Beyond3D News
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    After too long a hiatus, we're back with a new GPU and architecture analysis! ATI's 40nm marvel, RV740, is under Alex's microscope in Radeon HD 4770 form. Bringing almost everything that made RV770 (and now RV870) great to the lower end of the market, does RV740 ultimately impress?

    Read the full news item
     
  2. rpg.314

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    Thank God. You guys finally do a review. :) Better late than never.

    I guess this means that a rv770 review is nuked. Let's hope you guys can deliver a rv870 review, even if it is late.
     
  3. AlBran

    AlBran Ferro-Fibrous
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  4. Rys

    Rys PowerVR
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    RV770 board-level review is nuked, but the deeper arch piece isn't (since we'll just combined that with RV870's latest improvements into one thing). HD 5870 is done and I'm in the editing phase with Alex now.
     
  5. rpg.314

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  6. LordEC911

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    Dang, another review to read...
    Haven't even got through all the 58x0 reviews yet.
     
  7. AlBran

    AlBran Ferro-Fibrous
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    Are you complaining about having to read a Beyond3D article.:shocked: :wink3: :runaway: :runaway: :runaway:

    Although if *recent* history serves *correctly* *cough*, you'll have plenty of time to catch up until the next one. :wink4:
     
  8. wishiknew

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    I haven't checked the front page in a year and I hit jackpot!
     
  9. mczak

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    Not that I know of. But I think you're interpreting that wrong, docs say storage is separated per element. Hence you can access 3 .x components, 3 different .y components etc. (with some limitations) which is fulfilled by that instruction (x 2/3/13, y 3/13, z 3/16, w 0/3/16).
     
  10. trinibwoy

    trinibwoy Meh
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    Nice job guys, keep em coming.
     
  11. Jawed

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    Errors on page 9

    Both types can share an instruction group.

    T unit is fully functional while XY or ZW or XYZW unit-combinations are executing double-precision instructions. T is only subject to operand bandwidth/register-file porting.

    Order of work-assignment (XYZW versus T) is actually an option in the hardware: CONFIG.ALU_INST_PREFER_VECTOR.

    T: can also use any of the in-pipe registers: PV and PS, or any type of constant. The operand fetching algorithm and resulting constraints are byzantine and not worth the effort comprehending (unless you're writing a compiler or are after the last 1% of performance).

    "Owner-exclusive" is merely an option. Though I've seen one document that suggests otherwise, it's battling both the R700 Family ISA and the Intermediate Language Specification (which, admittedly, could be considered "forward looking", beyond R700).

    Jawed
     
  12. Freak'n Big Panda

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    Holy crap. amazing. Keep it up rys, I'm hoping for a 870 review.
     
  13. Richard

    Richard Mord's imaginary friend
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    This is Alex's fault. :eek:
     
  14. mboeller

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    not this time:

    http://www.beyond3d.com/content/reviews/53/1

    two for the prize of one ;)
     
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