Anyone know what the original K8 core design was like?

P

phynicle

Newcomer
i remember off somewhere before the offical annoucement of the AMD K8 family processors , that the core had undergone major design changes due to some reason and the hammer we've come to recognise now wasn't the one originally intended but actually a crippled version of a more glorified dream

can anyone tell me if i'm right or not?
 
I believe you are.

The original design wasn't the K7 on steriods. It was a RISC/CISC/VLIW architecture. I don't know anything else about it, except that is what we'll be seeing in K9 most likely. The person who was heading this -can't remember the name- left AMD - I think.
 
Saem said:
The original design wasn't the K7 on steriods. It was a RISC/CISC/VLIW architecture. I don't know anything else about it, except that is what we'll be seeing in K9 most likely. The person who was heading this -can't remember the name- left AMD - I think.
Click to expand...

Hmm.. I seem to remember that the design for the K8 was based on the K6 core and was CMP.. The name Raza Atiq is in my head for some reason.. not 100% sure, but I am sure that origionally the K8 wasn't based on the K7 core.
 
hmmm based on the K6 core...i really don't think so
as far as i can remember the hammer we're hearing now is more or less a cippled version of AMD's roiginal intensions.....in fact i think ....ahhh can't remember
 
The only things that are crippled is the register based (as opposed to the stack based x87) FPU instructions, which originally were supposed to be 3-address. AMD probably realised that SSE-2 compatibility is more important than the extra 10-20% performance. And of course they also added extra registers in 64bit mode.

Cheers
Gubbi
 
phynicle said:
hmmm based on the K6 core...i really don't think so
as far as i can remember the hammer we're hearing now is more or less a cippled version of AMD's roiginal intensions.....in fact i think ....ahhh can't remember
Click to expand...

Wanta bet? :) The K8's origional core engineering group was the same group that designed the K6. They eventually, and obviously, moved to the K7 for a technical foundation, but advanced planning - AFAIK - was based on the K6 core.

What I'm talking of predates the downgrade in preformance that their speaking of.
 
i can remeber that one of the main engineer walked off and if you look through the patents AMD put through
alot of the ones relating to the Hammer technology was under his name

and i'm still convinced that the original design was surprior coz i remember hearing th official annoucement of the hammer and was disappointed since i've already seen some features of what they were originally gonna implement....i know what i saw was the real thing because what they sed was going to be in the final version of hammer really did appear at the day of the annoucement...so credibility was there

but none the less i really like to know for sure from someone who really did know about this issue
 
That is a bunch of speculation based on a few patents AMD has.

Like I said before, the original K8 was a hybrid VLIW/CISC/RISC MPU. This is what I got from RWT, the posters there tend to be in the know. I haven't seen anything beyond that.
 
Ok, I appologize, I was wrong... I asked Josh - who runs Penstarsys.com - what it is that he knew and he replied:

From what I remember, the initial groundwork was laid by the K6 team, but it has always been based on the then new K7 core. Once the K7 was done, the design teams were mixed around, with some of the K7 people going to K8 and vice versa (or so I hear). But you are correct, the K6 team laid the groundwork based off of the K7. Now, the old K7 teams are probably laying down the groundwork for the K9, and I have a feeling that it will be a totally new architecture. What all it will be, I have no idea, but it should be interesting to say the least.
Click to expand...

So, I remembered the K6 was in there somewhere :) Kinda interesting none-the-less
 
i knew it i was half right...well thanx for the info anyways....hmmm k9's in development already...interesting
oh btw would it be a major core change to the K8 if they decide to support an extra memory interface?
 
i mean say if they were to add ...say support for DDRII , then the amount of changes they would have to implement into their memory controller...would be like alot?????
 
To my knowledge DDR-II specs haven't been finalized, so they would likely have a lot of trouble supporting it at this point in the game, besides, you'd have to verify all over again. =(

In the future, well I don't think it'll be as difficult, but I see it taking more time than simply coming out with a Northbridge revision and new motherboards.

Which leads me to think, how smart this entire integrated memory controller implementation really is.
 
i wonder the same thing
how good is this integrated mem controller
since the k8 will derive most of it's speed from it ite better be good
btw anyone have any ideas about the latency of on die controller compared to ones on motherboards?
 
Depends, if you're talking about how many MPUs, but it's roughly half. As the frequency of the clock scales the latency goes down, but it's by very, very little.
 
The presentations I have seen suggests 140ns for an on die memory controller vs. 220ns for state of the art north bridge (kt266a/333). This should translate into 15-20% increased performance. This more than makes up for a possibly segmented MPU market, where you have to support two standards (DDR I & II). It may even be possible for AMD to make one controller that can use both.

Cheers
Gubbi
 
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