AMD's "Trick" for Summer 2006

Brisbane is the city of my birth. What more do you need to know?

 

Are they making a secret AMD chip there?

 

Didnt they license some kind of special SRAM (ZRAM or something)?

 

That's implemented on the new K8L (Brisbane) to my understanding. And I think AMD has some 65nm Semprons coming shortly here, then the server market gets some 65nm love, and then K8L for H1'07.

 

Maybe a coprocessor from Clearspeed or Xilinx?
I remember reading about something along these lines...

 

That's the new big buzzword you'll read about tomorrow on TheInq.

 

None of you have guessed close. Nyah, nyah.

 

He says lobbing a grenade into the room and exiting quickly...

 

Well you all can keep guessing, but what ever it is being stressed as enthusiast only, so i really dont see how its going to matter if its a $1000 superchip and i doubt its going to close the 20%-30% gap conroe is going to do at a third of the price.


For the record Quad core and L3 cache are both garbage for a substantial instant performance boost. Likewise for the clock increase of another 200MHz. I had the pleasure of messing with a Northwood based EE, those had 2MB of L3 cache in addition to the 1MB L2. Suffice to say you dont get much out of it at all in gaming programs (I think it was like a max of 3% if anything at all). Its much more effective to boost your L1 or L2 cache. Further the cache the higher the latency of that cache.


Brisbane is 65nm Dual core and not scheduled for launch until 2007. 65nm production isnt suppose to start until late this year so its problably going to be 90nm. I'd go with the boosted L1 (1MB) and L2 (2MB) Cache's and maxed clocks personally. 3.0-3.2GHz Dual core maybe support for over DDR2 800MHz. It wont compete price wise though but that would sure make for a fast chip under AMDs current architecture.

 

You'd prefer a soggy cracker?

 

I say we take off and nuke the site from orbit - it's the only way to be sure...

(Sorry... Couldn't resist...)

 

Another reach: Could it be SLI memory?

 

No.

 

A very short thread on it:
http://www.beyond3d.com/forum/showthread.php?t=30843

 

Can anyone explain why AMD has not implemented a 256-bit wide bus to L2 cache yet?

The PIII had it years ago, and as far as I can remember the Athlon 64's are still using a 128-bit wide bus.

Don't you guys think that could boost performance significantly?

 

According to this article the link is 64bits in each direction (concurrently):

http://www.digit-life.com/articles2/mainboard/ddr2-800-am2.html

right near the bottom in the section "Instead of a conclusion".

Quite a damning article.

Jawed

 

Man, I am 0-2! AMD has some neat stuff coming down the road (Clearspeed, ZRam) but it is not one of those. Hmmm

 

The trick is reducing the price of the FX-62 to a third of what it is at the moment to match Conroe

http://www.hkepc.com/bbs/news.php?tid=604489

and still get beaten.

AMD has a trick up it's sleeve but Intel is busily sawing the arm off at the shoulder.

AMD has been on the gravy train for too long, if Intel can produce enough T6's and T7's then they are going to have to bleed all the way into 2007.

The gloves have finally come off.

Lets rumble.