AMD Phenom

LOL my wife is hot, my dog, lol, can't say too much, she is pug ;) , if it was my choice I would have gotten an alasken malamute
 
LOL my wife is hot, my dog, lol, can't say too much, she is pug ;) , if it was my choice I would have gotten an alasken malamute

We've two siberian huskies - compact wondeful dogs. Sorry for the OT but do love the doggies :)
 
i dont care what they'll call it if manages to have greater performance than intel c2d at a lower price they could name it ghey, pinc, laym etc.. i'd buy it anyway.
 
Well to me, it kinda sounds like venom, which is actually rather nice. "Phenom" as in phenomenal is kinda stupid.
 
Nothing is as bad as Core2Duo which not only is not catchy but hard to understand with it's 2 and duo in the same name.
 
AMD PhenomX4

I do know that AMD's advertising tune will be sung by the muppets..


phenomena -to du .. tududu..

phenomena ...

But I do wonder why they revert to an "om" ending after sempron, athlon, opteron, radeon, xilleon
 
I quite like it, especially when combines with the model name, i.e. X4, X2, FX.

Like XXX says, it sounds like Venom which is pretty cool. Its gives the impression of speed which is no doubt what the creators intended.

Now if it goes and lays waste to the Core2 Duo (and hopefully Penryn) then I think Phenom FX and Phenom X4 will sound pretty cool. Like Geo says though, its not quite as fitting if its slower!
 
Final AMD "Stars" Models Unveiled

4622largestarslistmj6.png


;)
 
There's something wierd going on there. Why do the 2 core and 4 core models have the same amounts of L3 cache?

If this is correct then that 2.3Ghz X2 looks like it could be a bargain. Seems to tally up strangely with the 2.2 Ghz version though as it has a lower TDP.

EDIT: forget it, I didn't realise that wa sa low power model, thought it was a budget model.

On the L3 cache, perhaps the 2MB size has something to do with keeping the lookup tables small and fast?
 
L3 cache in this new architecture is used [mostly] as a LRU flush container, aiding the smaller L2 portions to keep up with the coherent updates.
This "local L2 + shared L3" topology gives the best of the two worlds: optimal SMP efficiency (each core have its very own and rather big L2 pool) and low state/flush update latency in a single close-to-the-CPU place (the L3).
 
Back
Top