I don't think it matters who he is or his credentials; unless he physically changed the silicon, it's not currently possible in any shipping chips. There is only one "entry point" for setting multiplier on the entire CPU package, there is not any interface for multiplier changes on a per-core basis. And somehow "engineering" a way to do it would also require "engineering" a way to asynchronously reach the currently clock-shared L2 cache in at the same time.
And 3dilettante is right, and I had forgotten -- Intel has at least given the tech a name, but it still doesn't exist in production. Of course, being able to clock each core differently isn't much of a power saver if you can't volt them accordingly. And what are they doing with the shared cache architecture? Does it run full-speed full-time, or does it run at the speed of the highest-multiplier core currently active?
All of Intel's Pentium-M and later chips based on the banias / dothan / conroe / merom / etc & later tech have matching individual VID's for each multiplier. So either they're going to run the entire chip off the VID associated with the highest in-use multiplier, or else (hopefully, and more intelligently) they'll allow each core to request a different VID based on it's individual current multiplier. Of course, I wonder what that does for overclocking -- although i suppose they'll still allow "locking" of the multiplier (disabling of speed step)
Later Edit: Hey, you know what occurs to me? Your CompSi friend may be forcing throttling, which Intel does allow on a per-core basis. It's not a multiplier, but a forced level of clock-throttle. You can accomplish this through several means, I use a utility called RMClock to manage how my two laptops use voltage and multipliers. It also provides a force-throttle option, and I'm pretty sure it also allows it per-core.
