AMD: Navi Speculation, Rumours and Discussion [2019]

Discussion in 'Architecture and Products' started by Kaotik, Jan 2, 2019.

  1. PizzaKoma

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    http://www.freepatentsonline.com/10353591.html
    Fused shader programs
    Document Type and Number:
    United States Patent 1035359
    Assignee:
    Advanced Micro Devices, Inc. (Sunnyvale, CA, US)

    Abstract:
    Improvements in compute shader programs executed on parallel processing hardware are disclosed. An application or other entity defines a sequence of shader programs to execute. Each shader program defines inputs and outputs which would, if unmodified, execute as loads and stores to a general purpose memory, incurring high latency. A compiler combines the shader programs into groups that can operate in a lower-latency, but lower-capacity local data store memory. The boundaries of these combined shader programs are defined by several aspects including where memory barrier operations are to execute, whether combinations of shader programs can execute using only the local data store and not the global memory (except for initial reads and writes) and other aspects.
     
  2. PizzaKoma

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  3. del42sa

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  4. PizzaKoma

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    yes, 12 RDNA CU converts to 24 CU from the past generations in that regard
     
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  5. AlBran

    AlBran Ferro-Fibrous
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    I'm partial to identifying Navi CUs as D(ouble) CUs.
     
  6. del42sa

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    that is only partially true, because they can work together as workgroup or they can work independently....

    [​IMG]
     
  7. AlBran

    AlBran Ferro-Fibrous
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    Schrodinger's Cat Unit
     
  8. itsmydamnation

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    Are you tell me cats were harmed in the making of this GPU!!!! :runaway:
     
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  9. AlBran

    AlBran Ferro-Fibrous
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    Just needed a scratchpad... hm...
     
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  10. Tkumpathenurpahl

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    Yes and no.
     
  11. PizzaKoma

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    Probably for RDNA2 HPC chip or Arcturus? Uncertain about which thread this belongs in...
     
    #1272 PizzaKoma, Jul 28, 2019
    Last edited: Jul 28, 2019
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  12. Rootax

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    Is this a big deal for home users ?
     
  13. del42sa

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    HMC is pretty much a dead technology .... too expensive and too complicated

    https://www.micron.com/about/blog/2...t-in-high-performance-memory-roadmap-strategy
     
  14. Kaotik

    Kaotik Drunk Member
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  15. Silent_Buddha

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    Hmm? From the Micron Blog post by Andreas Schlapka (director of network technology in Micron's Compute and Networking Business Unit).

    And...

    So it would appear that Micron is moving away from HMC and investing more into HBM.

    I'd imagine existing customers could still get HBC, and if there was interest from a large player they might still make it for a new customer. But it sounds like they aren't putting any more R&D into it.

    Regards,
    SB
     
  16. Kaotik

    Kaotik Drunk Member
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    The "it" in my post was referring to the patent mentioned above, sorry for the confusion. I'm fully aware that HMC is dead and has been dead for some time
     
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  17. 3dilettante

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    As noted later, the claims don't discuss HMC. The method does sub-divide the stacked DRAM into vertical sections above a controller in a manner similar to HMC, but the memory interfaces with a GPU more like a form of LDS or distributed GDS.
    If a memory segment is above the CU requesting data, the data is fed vertically down directly to the register file, which is closer to how the LDS might work versus the vector cache hierarchy. If the memory is not above a local CU, there's a potentially separate mesh of cached interface stops that pass data to the requester.

    This patent came up earlier in the current thread: https://forum.beyond3d.com/posts/2075654/

    Whether this is going into any product like Arcturus or incoming GFX10 chips, there are some signs that it is less likely.
    For the GFX10 case, the claims discuss a SIMD16 GPU as an example that doesn't exclude a SIMD32 RDNA, but doesn't provide evidence for it being used either.
    For Arcturus, the code commits that mention it include hints that it's likely to be running near the thermal limits of GCN's power management (power scheduling is explicitly disabled, compiler code is notified to avoid certain instruction mixes to avoid throttling), and there's mention of it being associated with the name MI-100. If the existing 7nm Instinct chips serve as a starting point for extrapolation, this seems like it runs too hot for a 3D stack. Earlier presentations on TOP-PIM gave a power ceiling of ~15W for memory and the silicon below it.
    While there could be code changes in the future, neither GFX10 or Arcturus mention changes for a memory pool whose behavior may be very different from existing types. Vector memory in particular would have different rules, and I'm not sure the LDS/GDS changes indicate MB or GB of storage being made available.

    On top of all this, I noted the first time around that this comes from a Department of Energy research program into HPC, which going by the history of other such patents from DOE programs has either a low chance of being used or a long timeline for being seen. Some of the low-voltage and variable-SIMD patents that people were clamoring about in 2016 (filed in 2014) as possibly being Vega or Navi-related have not shown up for either three years later, so if the trend persists it won't be applicable to any chip currently in the rumors for the near or mid-term.
     
  18. PizzaKoma

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  19. PizzaKoma

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    Translation by google:
    "If 4096 SP Navi comes out this year, I think it is GFX1011 (Navi 12). Since the sample 7360:00 is already running, if it comes out this year, 12 will be correct in timing. I think next year there is also the possibility of GFX1030 (Navi 21?)."

    7360:XX is Navi 12 ?
     
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