AMD: Navi Speculation, Rumours and Discussion [2019]

Discussion in 'Architecture and Products' started by Kaotik, Jan 2, 2019.

  1. no-X

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    What is the source of the info? I'd say there is a 16 CU Navi die (with 12 CU cut-down version) and 10 CU Navi die (with 9 CU cut-down version). Combination of 14nm IO + 7nm Zen 2-chiplet + two different 7nm Navi-chiplets would allow immense flexibility. I'm sure the semi-custom division would love it. Btw. the 16 CU die could be also sold separately as dicrete low-end.
     
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  2. Cat Merc

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    One has to make a distinction between the rumors and the speculation. He clearly said he doesn't have information about how the dies are configured, and he said he's speculating about the APU using the same chiplets.
     
  3. ToTTenTranz

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    15-20% higher clocks than what? Vega 10? Vega 20?
     
  4. DmitryKo

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    20% higher than current base 1.5 GHz for Vega 20 - i.e. 1.8 GHz base and 2GHz boost for Navi 10.
     
  5. yuri

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    Anandtech asked AMD whether their next Zen2 based APU would be chiplet design or not. AMD replied it would not. So this means the 2020 7nm Zen2-based Renoir APU will not employ the chiplet + IO composition. It makes sense - margins would be tight laptop APUs.

    https://www.anandtech.com/show/1385...nt-on-matisse-cpu-tdp-range-same-as-ryzen2000 Let's hope this won't be another garbage info coming from Anand's...

    A GCN-based chip achieving 2GHz, 1.3 IPC of Vega with a sensible TDP sounds highly unlikely.
     
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  6. iMacmatician

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    According to netkas.org, the Navi strings do not represent different chips or products.

    There were strings in late 2016 containing "Polaris10," "Polaris12," "Polaris10XT2," and "Vega10," which apparently refer to codenames. That was a different file though.
     
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  7. DmitryKo

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    Who said 'IPC' or 'GCN'? ;)

    This could be the case if the source code uses virtual functions and overloading - but who really writes low level drivers in C++? :shock:
     
    #107 DmitryKo, Jan 21, 2019
    Last edited: Jan 21, 2019
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  8. mczak

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    Not sure what that 30%/40% refers to, but AMD is probably happy about how Turing turned out, because if you exclude the new features, its perf/area (or perf/transistor) is quite bad compared to Pascal (30% worse or so) (although it still does well against Vega, and at least perf/w didn't get worse). That'll give AMD some opportunity to catch up with Navi in theory, albeit for now I remain sceptical...
     
  9. w0lfram

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    Interesting to note, that when Vega (code name for chip) was released Dr Su said that the name was so "cool", that they would keep the "chip" name for marketing. Hence Radeon Vega X.

    The Card AMD announced at CES is a Radeon VII (Seven), no mention of Vega. Even though I have heard Dr Su herself, mention the Radeon Seven as Vega2 several times...

    Radeon VII was actually suppose to be Radeon Vega 2... (ie: Navi).
     
  10. Kaotik

    Kaotik Drunk Member
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    Renoir GFX9? Is there actual source for this? Only roadmap I've seen mentioning Renoir doesn't say anything about which architecture it would use for absolutely anything
     
  11. Kaotik

    Kaotik Drunk Member
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    Devil is in the details, they didn't actually say it won't be chiplet design, they said it wouldn't use Matisse design
     
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  12. Rys

    Rys AMD RTG
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    No.
     
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  13. CarstenS

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    Seeing the size of the I/O dies, even considering, they have a higher percentage of analogous circuirty and are in an older process tech, I wonder if they don't have enough space in them to at least provide „functional“ Vega GFX. Maybe nothing like 16 CUs or the like, but 4 to 8. OTOH, if that was the case, I cannot think of any sane reason for AMD not to announce APU parts at the same time, except maybe inventory.
     
  14. yuri

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    It sounds strange to me too but hey, their APU line tends to be lowcost.


    Oh, you are right.
     
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  15. del42sa

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    Navi being officially GCN since first announcement ;)
     
  16. DmitryKo

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    Well there were conflicting reports abot Navi being the last GCN or first post-GCN architecture... I just meant better efficiency overall, whether from IPC and scheduling, caches and data compression, or automatic primitive shaders, geometry binning and other features which couldn't work in Vega for some undisclosed reasons.

    RTX2070 only has 1/2 TFLOPS of Vega 64 yet it's 10% faster in real world applications... can't attribute it all to the voodoo magical tensor cores.
     
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  17. Rootax

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    Maybe tmu/rops too ? 64 is not a limited thing for Vega ?
     
  18. DmitryKo

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    Sure - every little tweak here and there, but primarily more efficient fixed-function blocks.

    I for one would expect a working primitive geometry shader stage with the promised 3-5x throughput over traditional triangle-based geometry, even though very little implementation details were provided to back this claim and there are still unanswered question about the scope of possible API/DDI refactoring needed to achieve the claimed gains.
     
    #118 DmitryKo, Jan 22, 2019
    Last edited: Jan 22, 2019
  19. no-X

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    Radeon VII and GeForce RTX 2080 have almost the same transistor budget and Radeon VII is expected to perform just a bit worse than GeForce RTX 2080. That doesn't indicate any architectural problem at all. The only problem is lower energy efficiency. Performace per transisor at the same clock is very close.
     
  20. vipa899

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    I seriously doubt that.
     
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