AMD: Navi Speculation, Rumours and Discussion [2019]

Discussion in 'Architecture and Products' started by Kaotik, Jan 2, 2019.

  1. gamervivek

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    So Navi 10,12 and 14. Is it confirmed that 5700 is Navi 10? I'm guessing linux patches majorly address Navi10 and so would be for the first chip's release.

    Because looking back at rumors, they had three Navi chips, 20, 12 and 10.

    [​IMG]

    Navi 12 had 40CUs and was supposed to come in at Vega56.

    wccftech had an article in November where they said that the 40CUs chip was the first Navi and probably took the codename from above.

    Though the CUs for Navi10 from above vs. Navi20 don't make sense, unless Navi20 is like Vega20 on improved process.Or probably confused with Vega20 itself looking at the performance with the given CUs?

    And also four Navi variants from MacOS,
    https://wccftech.com/four-amd-navi-gpu-variants-leaked-rumored-for-july-2019-launch/

    Then we had a rumor four months back that Navi release had been pushed back to October. Maybe confusing it with the next Navi's release?
     
  2. JoeJ

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    Seems very similar to RTX, as far as i can imagine how the latter works.
    No FF ray reordering / batching is mentioned. The flexibilty options coming from interaction with general shaders likely boil down to what DXR offers: Batch the rays as good as you can yourself in the ray generation shader.
    (After all my initial critique, i'm quite fine with that. Reordering likely is something for the post hybrid era, and without it the costs in die area make sense.)

    I really wonder how they manage a stack per ray. Can one assume an upper bound of how large this stack has to be? And even if, that's a lot of memory and bandwidth.
    Personally i've always used stackless approach on GPU. I must be missing something here...
     
  3. del42sa

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    using AdoredTV chart as reference is really good idea :-D
     
  4. snc

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    "Fixed function ray intersection engine in a texture processor" - question, this texture processor in amd nomenclature is tmu or some sort of CU ?
     
  5. CarstenS

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    That's how articles about the Navi reveal at AMDs techday say it, yes.
     
  6. anexanhume

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    It's on an official AMD slide.
     
  7. Dictator

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  8. ToTTenTranz

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    So.. BVH calculations on RT'ed Navi are done on the TMUs?

    Won't this create a bottleneck on texture mapping throughput?
     
  9. Globalisateur

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    So is RT on Navi going to be:

    Hardware* accelerated Ray Tracing

    * Using the available TMUs (hey that's hardware stuff) available on GPUs
     
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  10. ethernity

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  11. no-X

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    Well, framerate is often halved with RT enabled, so half of the TMUs should be available without any additional bottleneck ;-)
     
  12. Malo

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    Did we really expect Navi to have anything for RT beyond a new innovative use of existing hardware? I don't expect consoles to have anything beyond this either.
     
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  13. Rootax

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    How is this not doable on Vega ?
     
  14. ToTTenTranz

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    Seems like a method to stack an APU or GPU with HBM using TSVs.
    I keep reminding myself of that patent that mentioned a method to dissipate the heat of a chip across the PCB with copper tubes.
    Stacking HBM with an APU would be great to reduce costs, but the problem of dissipating the heat between the stacks should prevent it from happening.

    Maybe this way they could do it.

    [​IMG]
     
  15. anexanhume

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    Like this

     
  16. snc

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    Probably lack of ray intersection engines in texture processor doesn't help
     
  17. Rootax

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    Reading the patent, I've a hard time figuring out if the ray intersection engine is a dedicated hardware engine, or just a "concept"/step for calculations done by existing units.
     
  18. snc

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    "Fixed function ray intersection engine" - fixed function so hw
     
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  19. Rootax

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    Ah f***, how did I miss that... The heat wave in France is getting me : o

    Thx :)
     
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