AMD: Navi Speculation, Rumours and Discussion [2019]

Discussion in 'Architecture and Products' started by Kaotik, Jan 2, 2019.

  1. function

    function None functional
    Legend Veteran

    Joined:
    Mar 27, 2003
    Messages:
    5,135
    Likes Received:
    2,248
    Location:
    Wrong thread
    Yeah I made a mess of that. :sad2:

    Thanks folks.
     
  2. del42sa

    Newcomer

    Joined:
    Jun 29, 2017
    Messages:
    166
    Likes Received:
    82
    I see one potential issue with that announced 1,5 perf/watt. value.

    We know that 1,25perf/watt. for Navi is given by the process, it´s the same case as with Vega 20, it´s logical. AMD made some architecture change within NAVI so that RDNA is responsible for 1,25x/clock performance increase. Problem is, that AMD declares "up-to" value. It could mean, that Navi will not always achieve it´s 1,25x performance but it could be less, depending on workload. Who remember announced 2,5 perf/watt. for Polaris would understand, what I mean. The performance growth was not related to the entire line, but only to a particular comparison between RX470 vs R290.

    In the end it may be that in some games the gain will be greater and in others just a few percent above GCN Vega, clock to clock performance.
     
  3. ToTTenTranz

    Legend Veteran Subscriber

    Joined:
    Jul 7, 2008
    Messages:
    9,844
    Likes Received:
    4,457
    And the transistors needed to provide the 25% IPC increase probably don't come at zero power cost.
    Perhaps a hypothetical 14/12nm Navi with GDDR6 would "only" be 1.2x more efficient than Vega 10.
     
    del42sa likes this.
  4. CarstenS

    Veteran Subscriber

    Joined:
    May 31, 2002
    Messages:
    4,797
    Likes Received:
    2,056
    Location:
    Germany
    Was it established already, which hardware level the increased IPC is referring to? Per SIMD, per CU, per SE, per GPU?
     
  5. Urian

    Regular

    Joined:
    Aug 23, 2003
    Messages:
    621
    Likes Received:
    55
    I am the one who made the original article that reddit linked.

    I made clear in my own article that I could be wrong at 100% and this is a speculation with the few info that we have.

    Since is only partially informed speculation I am not going to add anything or say anything about it.
     
    w0lfram, Jay, Alexko and 3 others like this.
  6. ToTTenTranz

    Legend Veteran Subscriber

    Joined:
    Jul 7, 2008
    Messages:
    9,844
    Likes Received:
    4,457
    Nope.
    Current rumors have been pointing to Navi 10 being a chip with 8 shader engines x 5 CU each, in which case there would be a significant increase in front-end width compared to Vega 10.
    AMD mentioned a revamped cache subsystem so I'd guess that would be at the SE level. There are also rumors of RDNA using Super SIMD, but I think it's mostly because of the patents that have come up in the last couple of years.
     
  7. Urian

    Regular

    Joined:
    Aug 23, 2003
    Messages:
    621
    Likes Received:
    55
    And I forgot something to add...

    1. I never said in my blog post that the Super-SIMD only would give the hability for Real Time Raytracing. I made clear in it that Traversal Unit/RT Cores would be needed.
    2. In my blog post I talk about the possibility of AMD adding some of the AI accelerators from Cadence. But i never specified as "for Xbox Next only".
    Thanks for your time.
     
    ZoinKs!, BRiT, Jay and 4 others like this.
  8. 3dilettante

    Legend Alpha

    Joined:
    Sep 15, 2003
    Messages:
    8,122
    Likes Received:
    2,873
    Location:
    Well within 3d
    For clarity, I am not disagreeing about it being possible for there to be changes in how instructions are issued.
    I was stating that my (also speculative) interpretation of the github changes concerning the caches has them discussing a different part of the architecture.
     
    Urian likes this.
  9. w0lfram

    Newcomer

    Joined:
    Aug 7, 2017
    Messages:
    156
    Likes Received:
    32
    [​IMG]


    ...and High Clock Speed...!


    Anyone want to guess what Navi could reasonably be clocked at?
     
  10. Frenetic Pony

    Regular Newcomer

    Joined:
    Nov 12, 2011
    Messages:
    322
    Likes Received:
    82
    Already calculated that to be a bit above a Radeon VII (1750mghz), assuming there's 40cu.

    Frankly I just hope there's raytracing/extra feature support, that's not a small die for the 7nm node.
     
  11. bridgman

    Newcomer Subscriber

    Joined:
    Dec 1, 2007
    Messages:
    58
    Likes Received:
    102
    Location:
    Toronto-ish
    I don't think I said "rebuilt every block"... I was just trying to make the point that changes in the underlying implementation did not necessarily have to be driver-visible.

    When the first GCN parts were launched we talked about ISA and implementation without drawing a line between them... so while we have generally thought about GCN as a programming model / ISA a lot of people seemed to be thinking about "GCN" as a micro-architecture instead.

    Is your question about definition of GCN ISA or definition of GCN micro-architecture ? Probably can't answer yet either way but at least we can get closer on the question :D
     
    Cat Merc, DeeJayBump, Gubbi and 14 others like this.
  12. 3dilettante

    Legend Alpha

    Joined:
    Sep 15, 2003
    Messages:
    8,122
    Likes Received:
    2,873
    Location:
    Well within 3d
    I do wish for more clarity on what AMD thinks GCN is, then determining what features distinguish RDNA--and at what level it is different from what came before.
    I would like to go with a clear discussion that recognizes a distinction between architecture versus microarchitecture, though it seems from the outset it was glossed over with Tahiti.
    I've commented in the past on how I felt the descriptions of GCN disseminated to the public had a lot of what I'd consider implementation details versus the architecture presented to software.

    Is this current distinction focused primarily on the GCN ISA and CUs, or can there be a distinction based on the hardware not in the CU arrays?

    Even going by ISA, it seems like GCN is notably less static than CPU ISAs over time, as evidenced by new encodings for scalar memory ops, swaths of the vector ISA encodings moving to new locations in the opcode space, and Vega fiddling with the naming and encodings for some FMA operations.
    I'm not sure what can be commented on about the LLVM changes documenting GFX10's moving swaths of the vector ISA back to GFX6/GFX7 placement.

    So is GCN strongly linked to the ISA, or is there more of a "theme" given how much of the ISA has shifted despite the GCN name being maintained?
     
    Nemo, del42sa, pharma and 1 other person like this.
  13. del42sa

    Newcomer

    Joined:
    Jun 29, 2017
    Messages:
    166
    Likes Received:
    82
    yes, and that was the whole point of that discussion, wasn't it ? That Polaris is different enough than previous GCN chips and here we go again with NAVI being RDNA :-D
     
  14. AlBran

    AlBran Ferro-Fibrous
    Moderator Legend

    Joined:
    Feb 29, 2004
    Messages:
    20,658
    Likes Received:
    5,758
    Location:
    ಠ_ಠ
    Wonder if we might eventually see consumer cards with a modest amount of SSD (ala Radeon Pro SSG).
     
    Per Lindstrom likes this.
  15. LordEC911

    Regular

    Joined:
    Nov 25, 2007
    Messages:
    788
    Likes Received:
    74
    Location:
    'Zona
    Wrong.
    https://www.anandtech.com/show/1441...ducts-rx-5700-series-in-july-25-improved-perf


    We have already heard about clockspeed regression on this process and future ones, where they need to do significant work to overcome the inherent shortcomings.
    So the question is, doing that required work- did they move the needle to the "new" edge of the chip's capability or did they place it in a more "comfortable" position in regard to voltage/power efficiency or somewhere in the middle?

    Based on the 1.25% IPC and assuming 40CUs, one could assume that chip would need clocks ~10-15% higher than Vega 20 to end up around a RTX2070 (plus I think 2ghz would be a milestone AMD would strive for).
    So something like 1600-1650mhz base and ~2ghz boost. IMO- those clocks would be somewhere in the middle, leaning slightly more towards the edge.
    If it is 48CUs then with the 1.25% IPC, AMD wouldn't have to push the clocks as much and likely could leave it around Vega 20 clocks and get their ~50% increased power efficiency that way.
    Say 1500-1550mhz base and 1800-1850mhz boost.
     
    #635 LordEC911, Jun 3, 2019
    Last edited: Jun 3, 2019
  16. del42sa

    Newcomer

    Joined:
    Jun 29, 2017
    Messages:
    166
    Likes Received:
    82
  17. AlBran

    AlBran Ferro-Fibrous
    Moderator Legend

    Joined:
    Feb 29, 2004
    Messages:
    20,658
    Likes Received:
    5,758
    Location:
    ಠ_ಠ
    BRiT likes this.
  18. BoMbY

    Newcomer

    Joined:
    Aug 31, 2017
    Messages:
    68
    Likes Received:
    31
    Not necessarily, simple RT could be implemented without many changes: http://diglib.eg.org/handle/10.2312/hpg.20141091.029-040

    Of course dedicated circuits would be better. They could also do it like in the paper, and then reserve a fixed amount of CUs do to RT in parallel to the normal pipeline, or whatever.
     
    OCASM likes this.
  19. w0lfram

    Newcomer

    Joined:
    Aug 7, 2017
    Messages:
    156
    Likes Received:
    32
    It depends on what the base freq of Navi will be. I think She said several times they worked hard on clocks, and she says "higher freq" several times in her keynote and with it written on banners. Hence, "and high clocks speeds..!" quote.



    I don't see anything wrong with suggesting that Navi can't hit 2,100Mhz at 7nm. I think Dr Su is a study of AMD past and like to topple stigmata. But there might be more to it than just freq.
     
  20. Frenetic Pony

    Regular Newcomer

    Joined:
    Nov 12, 2011
    Messages:
    322
    Likes Received:
    82
    High clocks speeds should be expected. Vega was supposed to hit high clockspeeds but failed, causing some exponential power spikage that seems partially independent of silicon node. Hence why Vega 64 missed its clockspeed targets and the Vega arch gets way more efficient at the low clockspeeds found on mobile parts.

    Thus any improvements to clockspeed from 7nm can't be inferred from the Vega VII, that things huge powerdraw is due to arch, not the fmax curve of TSMC's 7nm. Going by TSMC's own numbers 7nm vs 16nm should be a huge improvement in TDP efficiency for AMD. Thus the low quoted efficiency improvements could easily be due to maxxing out clockspeed with no regards to powerdraw for a desktop part, a strategy which AMD just recently said sells better. Besides, the quote for 1.5x improvement was "at least" meaning it'll probably get much better for whatever laptop part they have replacing the Vega 10.
     
Loading...

Share This Page

  • About Us

    Beyond3D has been around for over a decade and prides itself on being the best place on the web for in-depth, technically-driven discussion and analysis of 3D graphics hardware. If you love pixels and transistors, you've come to the right place!

    Beyond3D is proudly published by GPU Tools Ltd.
Loading...