No need for snark. Come on, grow up. If you don't have anything tangible to discuss, then save the attitude.
AMD: Navi Speculation, Rumours and Discussion [2019-2020]
- Thread starter Kaotik
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No need for snark. Come on, grow up. If you don't have anything tangible to discuss, then save the attitude.
Bondrewd
Veteran
Everything you need to know is hidden inside XSX SoC.
:^)
Engineering.
Quite a lot of it.
:^)
I genuinely mean it.
Engineering.
Quite a lot of it.
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Perhaps, though we are talking about a part that is twice as large as that.
Even typical nVidia level of magic puts their highest end at 1.5GHz compared to more modest retail units at higher GHz. Something has to give.
Bondrewd
Veteran
Which also has twice as much power allocated to all things GPU, yes.
Remember, these are the first console SoCs in years to carry non-joke CPUs.
55-60W Zen2 (Renoir case for that) configs are fat.
And they chew power.
But you just said it was 275W, not in the 400W range. So which is it?
There's a non-linear relationship with clocks & voltage.
Bondrewd
Veteran
I never said PS5 GPU was 200W.
I think he's implying compared to PS5s GPU that 275W would be double. Which I honestly doubt.
Bondrewd
Veteran
You have your rights to, and AMD has the prowess to prove everyone wrong (maybe even me).
Yay.
I'm still waiting for you to post even some speculation tweet or something to back your words, so far I've seen you post nothing to back your words despite always wording your posts like they're facts
He does seem quite confident doesn’t he? We’re all gonna be super impressed with RDNA2 or victims of a very persistent troll campaign. I hope it’s the former.
XSX GPU clocks are lower than the majority of RDNA1 boost clocks though including Navi 14.
Bondrewd
Veteran
Less than AMD anyway.
Yeah.
Yeah.
The thing smashed my estimates, and I'll smash yours (same for Zen3, too).
Too bad the availability will be made of suck.
It also has a vastly bigger config than anything Navi1x, being 52CU and 320b mem.
At very funny wattage.
It's not Boost-clock for XSX though, but constant aka "baseclock with no boost"
Well in that case it's about 100-150 MHz higher than RDNA1. Isn't exactly ground breaking.
Komachi and an Asian supply chain source seem to be teasing Navi 3X being a multi-die design, splitting into GCD (presumably Graphics Compute[?] Die) and MCD.
If I were to guess, controllers and PHYs for display, memory and DMA would get spun off as MCD, and get manufactured a different process. Memory-side L2 stays on the monolithic GCD die, so as the gigantic L1-L2 interconnect.
Then the interconnect between the two dies would need only as much bandwidth as the GPU memory pool can deliver (maybe except when multi-GPU is enabled), which is totally viable in today's TSV packaging tech (equivalent to HBM class bandwidth).
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Frenetic Pony
Veteran
Komachi and an Asian supply chain source seem to be teasing Navi 3X being a multi-die design, splitting in GCD (presumably Graphics Core[?] Die) and MCD (presumably Memory Controller Die?).
That's a perfectly achievable first goal, though it would seem to eliminate their current, "tiled" memory design, which already seemed poised for chiplets.
That being said, how much die space does that split off? I know memory controllers aren't small, but I can't find any estimates.
Navi 10
If we assume the annotations in this Reddit post are accurate, shader arrays and the associated graphics functions occupy ~55%.
Bondrewd
Veteran
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Nebuchadnezzar
Legend
Remember that the % would be bigger for a bigger die as the remaining media bloat would stay at a relatively fixed size - at least in theory. The savings wouldn't be also exactly 45% as you'd need to re-add the SerDes with enough bandwidth to the IO die, which would be significantly wider than what we see in Zen2 to be able to feed enough bandwidth. I don't know how much space that'd be but I imagine at least half the size of the current memory PHYs. Obviously that's still around a 30% die savings for a GPU of that class - probably worth it for cost savings and yields.
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