AMD IP in Intel next-gen IGP

Discussion in 'Architecture and Products' started by CarstenS, Dec 6, 2016.

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  1. CarstenS

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  2. AlBran

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    What could it be/entail?

    Something minor/annoying? :p
     
  3. ToTTenTranz

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    "Putting AMD tech into Intel's iGPU" could be something as small as an IP block that is completely transparent to the user like something to accelerate delta color compression.

    IIRC, @Andrew Lauritzen said there's no async compute capability in Intel's iGPUs because they're so small there hasn't been a strong enough motive to work on that implementation. Perhaps that's about to change and Intel is looking at cutting some corners by using some AMD GPU IP.
     
  4. CSI PC

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    Is this really a smart move by AMD when they are looking to compete against Intel in terms of their latest APUs, fingers crossed it is not just about the cash for AMD.
    Will be interesting if any details leak.
    Cheers
     
  5. Ike Turner

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    Fun Fact: Andrew just left Intel and is joining DICE/FROSTBITE in January:
    https://twitter.com/AndrewLauritzen/status/806222972318949376
     
  6. homerdog

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  7. CarstenS

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    My 2 cents: patents and safeguarding against lawsuits. Delta-C compression is already in skylake, FWIW.
     
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  8. jiaolu

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    I have a hunch that intel just license the amd gcn instruction set, and make sure the amd future gpu maintain instruction backward compatibilities. which sony and Microsoft already push the amd future gpu to to be designed this way. the whole thing already not unlike the x86/x64 instruction license between two companies.

    The intel will continue design their own gpu embedded in cpu and maintain the gpu drivers, of course with the head start help of amd open sourced gcn compiler in llvm.

    the ripple effect is the gcn instruction may be the definition of gpu instruction, just like x86/x64 today. and huge blow to the NVidia gpu business.
     
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  9. jiaolu

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    I also suspect APPLE play a hand in this with its obsession of single standard all the way, and push the intel/amd to their data center solution.
     
  10. MDolenc

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    You're already way off track here. GCN already isn't 100% compatible between iterations (some instructions are added, some instructions are removed).
     
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  11. jiaolu

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    not sure how much vega isa differs with (polaris)GCN 1.3 . Or Vega gen ISA will be used as the start point as ISA standard.
    my speculation is these will be all for GPU compute ISA. Graphics pipeline will evolve in their own path.

    the evolvement of GPU ISA could be agreed on particular policy. the latest x86/x64 will not look like 8080 isa code。
     
    #11 jiaolu, Dec 8, 2016
    Last edited: Dec 8, 2016
  12. MDolenc

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    x86 has weight because there's a ton of software compiled and shipped. There is no GCN compiled and shipped code on PC. You don't even have the mechanics to do that (on consoles you have). AFAIK not even with Mantle. If you want to talk with GPU from a modern graphics API you'll have to use SPIR-V (Vulkan) or DXBC/DXIL (DirectX). GPU ISA is completely hidden.
     
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  13. sebbbi

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    Since last summer you have also been able to write GCN assembly on PC:
    http://gpuopen.com/amdgcn-assembly/

    However there's not a single game or consumer application that does it. So no legacy code to care about. GCN assembly seems to be targeted to researchers trying new stuff (academic papers, not shippable code). It could also be usable in HPC applications (guaranteed to run on certain GPU configuration). ROCm isn't the most popular API after all :)

    I respect AMD a lot about the openness. Highly detailed GPU ISA docs are available for each GCN generation and now also ROCm allowing developers to directly write GPU assembly code and execute it on PC. Tools like CodeXL give also good insight about the shader compiler. Allows the developer to inspect the generated assembly code, register counts, etc. Unfortunately Nvidia isn't as open. You have to guess how their GPUs operate and guess why some of your shaders runs slowly. They have some nice documents about best practices, but it can be hard to identify the exact bottleneck without low level knowledge of the hardware and low level tools exposing the hardware bottlenecks.
     
    #13 sebbbi, Dec 8, 2016
    Last edited: Dec 8, 2016
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