AMD Carrizo / Toronto

Discussion in 'PC Industry' started by Alexko, Dec 25, 2013.

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  1. Alexko

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    Here's the first concrete bit of information about Carrizo, for now only known for sure by the codename of its server variant, Toronto:

    http://insidehpc.com/2013/12/22/hsas-clusters/

    • 4 Excavator cores;
    • Volcanic Islands graphics (whatever that means);
    • DDR3/4 support;
    • Integrated southbridge, in other words, it's a full SoC.

    The integrated southbridge probably means we can kiss FM2+ compatibility goodbye, but on the upside, it should save a bit of power and enable more compact form factors. The chip might even make it into a few tablets, if that's your cup of tea. I wonder how well all the southbridge I/O and ~4GHz logic are going to play together on the same die.
     
  2. Kaotik

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    Latest rumors are saying that Carrizo would feature Stacked DRAM. This would fit the fact that AMD is working with Hynix on HBM memory that's supposedly ready to be used in 2015

    edit: Also, "Volcanic Islands graphics" means Tonga/Iceland level, one step newer than Tahiti/Bonaire (which are Sea Islands)
     
  3. Wynix

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    I hope they have done something to tackle their bandwidth problem.
     
  4. Alexko

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    One thing that makes me skeptical about HBM in Carrizo is the fact that AMD said HBM would come to GPUs first and APUs second. Given that there is no rumor of HBM in any upcoming GPU this year, that's not a good sign.

    Then again, we know nothing of Fiji, and plans sometimes change.

    Yes, and fixing their latency problem wouldn't hurt either.
     
    #4 Alexko, Jul 15, 2014
    Last edited by a moderator: Jul 15, 2014
  5. ToTTenTranz

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    Why would they use HBM on GPUs first if lack of bandwidth is clearly a much bigger problem for APUs?
     
  6. Alexko

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    I can't speak for AMD, but bandwidth is a pretty big problem for GPUs too. They solve it with very wide buses and very high-speed GDDR5, but that's costly (power, die area, board complexity).

    And I don't know how costly HBM is at this point, but if it's a lot, that might be easier to absorb on $500 graphics cards than on $100 APUs.
     
  7. Kaotik

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    HBM for Fiji this year and Carrizo next?
     
  8. Alexko

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    Yeah, that's the only way to make everything fit, but there's nothing concrete to support this at this point.
     
  9. rpg.314

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    They have more margins on GPUs, especially high end ones, they can absorb the cost increase better than an APU, where AMD has to play in the low end segment which is more price conscious.
     
  10. Alexko

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    Some information:

    [​IMG]
    http://www.computerbase.de/2014-07/amd-carrizo-mit-hdmi-2.0-und-voller-hsa-unterstuetzung/

    I don't speak German but if Google translation is to be trusted it mentions +30% performance at 15W, which is a bit odd since Kaveri starts at 17W for dual-cores and 19W for quads. It also seems to cite VR-Zone as a source but I see nothing on VR-Zone's website.

    The interesting part is that there's only 2MB of L2, vs. 4MB on Kaveri. One wouldn't expect this unless there were some way of compensating for the loss of cache, namely HBM.

    I'm also a bit skeptical of Carrizo's value at 12W where I'd expect low-power APUs (I think they're called Nolan and Amur) to do better.

    The part about "hi-perf bus" is vague but hopefully that means HSA is implemented efficiently this time. Finally, I find the lack of hardware support for h.265 a bit disappointing.
     
  11. ToTTenTranz

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    AMD has to play in the low-end segment for APUs because they can't properly value the advantage of their iGPUs -> because the iGPUs lack in bandwidth -> because AMD has merely touched the issue of lack of bandwidth in iGPUs during the 3 years of APUs that we've had -> because apparently it's more profitable to just put all the money on discrete GPUs -> because they have to practice low-margins in their APUs -> because they can't properly value the advantage of their iGPUs -> because the iGPUs lack in bandwidth -> etc. etc.


    To me, this is so stupid.. Kaveri is such a wasted opportunity. Even if the added memory channels or GDDR5 or whatever brought up the APU's power budget for 40/45W and the motherboard price another $15-20, the product would still be immensely more interesting that what we have now.
    And now Carrizo is following in the exact same steps. Still stuck at dual-channel DDR3. Still no GDDR5 and still no HBM.
    Where exactly do they think they're going with this?

    And now they're focusing the development of HBM on discrete GPUs first, in which AMD has a much less threatened market? So stupid...
     
  12. Kaotik

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  13. mczak

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    Either that or a L3 cache, but there's nothing of that sort on the diagram neither.

    Yeah hopefully it means they got rid of the 3 different buses to the graphic parts.
    It is somewhat odd since it is described as UVD6 whereas the current generation (in Kaveri) is just UVD4. You'll have to wonder what else they could implement in 2 generations without supporting h.265... Maybe it's just missing.
     
  14. yuri

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    AMD's CPU parts of the 'high-perf APU' products have been not competitive since its dawn with Llano. This forced them to occupy low/mid market segments.

    Any non-standard/new memory technology is expensive. So I can't really imagine any premium priced APU with weak AMD CPU.
     
  15. 3dilettante

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    Potentially, the former provides guidance on the latter.
    Cutting a quad core's power consumption that low probably leads to a lower clock ceiling, which reduces the impact of a miss.

    The design is likely fighting for die space, given the addition of on-die IO and possible growth in other areas that had feature improvements. The L2 would have been a comparatively low-hanging fruit in buying a few mm2, and for that cherry-picked low power point, halving it might shave off a few fractions of a watt.

    Possibly because it's the only corner case where marketing can find a 30%.


    Or bandwidth is a physically difficult and expensive problem to crack. If the rumors concerning GDDR5M are true, it's one that dead-ended a decent chunk of Kaveri's die.
    Possibly, AMD's difficulty in deriving value from its advantage in IGPs is because the value of that advantage is being overblown. It has probably prevented Intel from completely obliterating AMD and all memory of it, and then salting the earth over the ashes, but there are limits to what it can do.
    That the majority of x86 CPUs with graphics are Intel indicates way too much of the market doesn't care enough, and maximizing the value of the IGP as desired apparently only works if one discards the value of the money it won't bring, at least for that segment.


    Maybe they've implemented the filters or directory structures to allow for better concurrent accesses and caching to coherent memory, improving on Onion+.
    There is mention of preemption, which HSA requires, and possibly there are other HSA requirements added.

    We can go back and note that AMD's marketing for Kaveri was that it had "HSA features", so there are various requirements like preemption in the provisional specification that no current APU can meet.
     
  16. pTmdfx

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    Which is unlikely. Each bus has its own corresponding application, for instance the high-bandwidth Garlic for the private video memory aperture, and I would wonder if there is any benefits to get a single one other than sounding better. Does not getting them in one break HSA either? No.
     
  17. pTmdfx

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    Given that GCN in Kaveri would not cache any coherent lines, I wouldn't hope much hope on this, but simply pushing the bar of bandwidth efficiency up. It would be interesting to know how the system architecture is compared with the SkyBridge APUs, as both fully support HSA as claimed.
     
  18. Wynix

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  19. Alexko

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    12W variants (assuming they materialize, which is not guaranteed since Kaveri was initially announced as a 15-35W chip and never went below 17W) are probably dual-core.

    According to Fottemberg (the author of the Italian article claiming that Carrizo would feature HBM) Carrizo is actually smaller than Kaveri. This may be due to the high-density libraries AMD was talking about—and the reduced L2, of course. Even if it were slightly bigger (thus more expensive) than Kaveri because of the southbridge, I don't think it would be a problem. I mean, OEMs have to pay for the southbridge either way, whether it's to the motherboard manufacturer or to AMD doesn't matter much.

    That would fit the pattern established with Kaveri; or any recent Intel chip, for that matter. I wouldn't call it a corner case, though. The laptop market is much bigger than the desktop market and I think even the ~15W market might be getting close to desktops, if not in volume, at least in revenue.
     
  20. 3dilettante

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    If the claims pan out, things like cutting half of Kaveri's oversized memory IOs would be a decent area saver. The IOs for HBM should be very small, if they are there.
    HDL might be a factor, but so can other things like if the 28nm process is different than the semi-custom one Kaveri is on. A full transition to a density-optimized node could allow for the GPU to shrink further, and also encourage a cap on CPU clocks.

    Should HBM be true, however, then AMD can be fighting for area savings because the dimensions of the chip and the HBM modules have an impact on the interposer and the package footprint. Even if the cheapest products can't justify the cost-adder, unless AMD has two different implementations, the chip has to be suitable for both.

    It could still be a corner case for the architecture, if it takes serious binning to get there.
     
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