Available at https://www.academia.edu/24842555/A_Survey_of_Cache_Bypassing_Techniques accepted in JLPEA 2016, reviews ~90 papers.
Part of the abstract: With increasing core-count, the cache demand of modern processors has also increased. However, due to strict area/power budgets and presence of poor data-locality workloads, blindly scaling cache capacity is both infeasible and ineffective. Cache bypassing is a promising technique to increase effective cache capacity without incurring power/area costs of a larger sized cache.
This paper presents a survey of cache bypassing techniques for CPUs, GPUs and CPU-GPU heterogeneous systems, and for caches designed with SRAM, non-volatile memory (NVM) and die-stacked DRAM. It covers bypassing techniques for inclusive, non-inclusive and exclusive cache hierarchies, and studies performed on both simulators and real-processors.
Part of the abstract: With increasing core-count, the cache demand of modern processors has also increased. However, due to strict area/power budgets and presence of poor data-locality workloads, blindly scaling cache capacity is both infeasible and ineffective. Cache bypassing is a promising technique to increase effective cache capacity without incurring power/area costs of a larger sized cache.
This paper presents a survey of cache bypassing techniques for CPUs, GPUs and CPU-GPU heterogeneous systems, and for caches designed with SRAM, non-volatile memory (NVM) and die-stacked DRAM. It covers bypassing techniques for inclusive, non-inclusive and exclusive cache hierarchies, and studies performed on both simulators and real-processors.