Hi,
I was reading about the BlueGene SC at wikipedia - http://en.wikipedia.org/wiki/BlueGene when i stumbled upon this sentence
"Each Compute or IO node is a single ASIC with associated DRAM memory chips. The ASIC integrates two 700 MHz PowerPC 440 embedded processors, each with a double-pipeline-double-precision Floating Point Unit (FPU), a cache sub-system with built-in DRAM controller and the logic to support multiple communication sub-systems. The dual FPUs give each BlueGene/L node a theoretical peak performance of 5.6 GFLOPS. Node CPUs are not cache coherent with one another."
the diagram that explains it
http://en.wikipedia.org/wiki/Image:Blue_Gene_L_ASIC.png
Now the PowerPC 440 is a General Purpose 32 bit RISC CPU, how can you put can such a compute node ASIC when it is made out of General-purpose hardware?
I was reading about the BlueGene SC at wikipedia - http://en.wikipedia.org/wiki/BlueGene when i stumbled upon this sentence
"Each Compute or IO node is a single ASIC with associated DRAM memory chips. The ASIC integrates two 700 MHz PowerPC 440 embedded processors, each with a double-pipeline-double-precision Floating Point Unit (FPU), a cache sub-system with built-in DRAM controller and the logic to support multiple communication sub-systems. The dual FPUs give each BlueGene/L node a theoretical peak performance of 5.6 GFLOPS. Node CPUs are not cache coherent with one another."
the diagram that explains it
http://en.wikipedia.org/wiki/Image:Blue_Gene_L_ASIC.png
Now the PowerPC 440 is a General Purpose 32 bit RISC CPU, how can you put can such a compute node ASIC when it is made out of General-purpose hardware?