2H2002 & 2003 developments: Look at TMSC process tech

CoolAsAMoose

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Some answers on what to expect in the near future (2H2002 and 2003) from NVidia, ATI, 3DLabs, Matrox and others should be able to get simply by looking at some specs of the process technogies of TMSC and UMC.

Example from TMSC (check it here):

"TSMC is working diligently on the 0.13-Micron process, with easy integration a top priority during its development. The new technology will reduce die size by more than 20 percent and provide performance improvements for 30 percent when it is compared to the same device on TSMC 0.15-Micron process technology."

Take the NV25, having 60 million transistors and running at 300 MHz. Reduction in die size of 20 percent gives 25 percent (1/(1-0.2)-1) more transistors for same die size. That would give us a 75 million transistor chip running at 390 MHz for the NV30 on the 0.13 micron process.

Ok, I'm fully aware of this calculation NOT being scientific in any sense, but I just wanted to have some numbers to throw around.


More interesting is, however, the improvements of their upcoming 0.09 micron process (check it out here):

"With 70-75% linear shrinkage and a two-times performance improvement, compared to TSMC's 0.13-Micron technology, Nexsys is poised to become the de-facto SoC process technology platform standard."

Using the 70% number, that would give us 3.3x the transistor count compared to the 0.13 micron process, with the same die size: 250 million transistors. And a speed of 780 MHz!!!!

Once again, this was a very simplified way of estimating the evolution, but still interesting. TMSCs 0.09 micron process seems to be ready to go later this year, so I guess we could see the NV40 on it 1H2003, or at least the NV45 in 2H2003.

So, do you think it's reasonable to think that we will see 250 million transistor GPUs running at 800 MHz during 2003?

If yes, what will these extra transistors be used for? I guess PS2.0 support will consume quite a few of them. Maybe 8 pixel pipelines, 8 (or more) vertex shaders - 8xVS@800MHz, that would be something for high-polycount games.

TMSC also seems to work quite a lot on eDRAM techologies. Will we see anyone using it for their 3D-chips?
 
NV25 has 63millions transistors then 25% more means 79 millions.

Interresting is that it has 8 metal layers. IIRC I read somewhere that the previous .15 micron process in use by nvidia has 4 metal layers.

Lets push a little more than maybe 90millions transistors at 400MHz. Now lets see the memory bandwith.
 
Since 9/13 is almost .7 I assume with 70-75% they mean something different than you ... meaning you get closer to 2x the number of transistors.
 
Nvidia and ATI have basically doubled their transistor counts ever year the last few years. I'd imagine something similar , maybe less, but I don't forsee NV30 having less than Parhelia because of PS 2.0 ....

Geforce1: 15 million transistors September 1999
GTS: 25 million transistors February 2000
Geforce3 57 million transistors February 2001
Geforce4 :63 million February 2002


Radeon 30 million transistor
8500: 60 million
 
Slightly OT, I wonder what Parhelia clock speed will be. Is they manage to get it into 275-300+ rage, my hat is off to Matrox.
 
so we are talking about fastest model here...
It was rumoured to be clocked at 300Mhz/DDR600

but when the 14th of May came closer, some rumours started to talk about 350Mhz/DDR700

and as they claim having 20GB/s bandwidth, they must have at least 312.5 Mhz / DDR325

I am thinking going 64MB version. I have doubled amount of GFX memory in every cycle:
1. Diamond Stealth 3D 2000 2MB
2. ATi Rage II 4MB & Voodoo 1 4MB
3. Matrox G200 8MB
4. Matrox G400 16MB
5. ATI AIW Radeon 32MB
and next would be logically:
6. Parhelia 64MB :)
 
Re: 2H2002 & 2003 developments: Look at TMSC process tec

CoolAsAMoose said:
so I guess we could see the NV40 on it 1H2003, or at least the NV45 in 2H2003.

We won't see NV30 until 2H2002, why would we see NV40 1H2003?
 
MfA said:
Since 9/13 is almost .7 I assume with 70-75% they mean something different than you ... meaning you get closer to 2x the number of transistors.

I read the TSMC news again.
The math is (9/13)*2 = .49 or two times and usually is never achieved.

The three times scalling factor maybe means a combination of the following:
- Excessive marketing/engineering optimism
- The current .13 micron process is not very good
- The future .09 micron process is excellent with many other geometricall rules scaling more than 9/13

Also it will use the 300mm wafers (more chips).

This is excellent news in the long term.
 
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