Early review of Quadro 2000, The overheating issue

[Typedef Enum]

Actually, that doesn't seem right either. nVidia never _targeted_ 500 MHz. with this product from the get go. As Anand stated, the early specs had NV30 hitting in the neighborhood of the 9700. It wasn't until the product slipped...and I might add, the likelihood of the 9700 introduction...that the thing suddenly turned into a 500 MHz. part.

I don't believe, for a second, that nVidia's goal all along was to bring out a part @ such a speed that it would require something along the lines of FlowFX to cool.

So, I feel that any issues that may crop up due to heat/noise is nVidia's fault...not the fault of the .13u process.

That one blurb about ATI/R350 was rather telling...Even TSMC was warning them against going with .13u, and this is quite likely why they chose to stick with .15u for the followup R350 part.

 

[Dave Baumann]

So, I feel that any issues that may crop up due to heat/noise is nVidia's fault...not the fault of the .13u process.

That might be an action of consequence. i.e. because of the lateness of the part due to .13u issues the clock speed was increased as to make it more of an attractive product in 2003 and/or it was increased because of the unexpected competetive environment at the time of its eventual release. In otherwords they needed to do something in an attempt to offset the fact the product was late caused by the process issues.

 

[Joe DeFuria]

Quincy said,

Um, JR, you mean my opnion of 3dfx? Common man let it rest, that Company is long gone. I really don't see how you can have a flame war invovling a company that no longer exsists.

Lol...how long has it been since you've ventured outside the console forum?

 

[Qroach]

Heheh, been a while. I couldn't help but commenting on the FX. It looks horrible on Nvidia for releasing that crap.

 

[Joe DeFuria]

Actually, that doesn't seem right either. nVidia never _targeted_ 500 MHz. with this product from the get go. As Anand stated, the early specs had NV30 hitting in the neighborhood of the 9700.

Hmmm...I thought Anand stated that the specs haven't changed since he was firt made aware of them about a year ago?

Curious...where (link) did Anand now say the specs have changed?

Personally, I subscribe to the following theory:

NVidia did originally target about 500 Mhz, but that would be on the low-k process. After the low-k didn't pan out nVidia had no choice but to produce it on the standard 0.13. Naturally, the target clock speed dropped a bit...perhaps to 9700 levles. However, after the 9700 shook up the market, they decided to "overclock" the NV30 (enter DustBbuster) to get it back up to the specs of the "original" low-k target.

I don't believe, for a second, that nVidia's goal all along was to bring out a part @ such a speed that it would require something along the lines of FlowFX to cool.

Agreed. However, my twist on this is that they didn't expect to require the FLowFX....based on a product made on 0.13 low-k dielectrics.

 

[KimB]

221 Celsius!!!!! They should take that card apart. Sounds like someone forgot to put thermal paste on it, or its not making contact to the heatsink.

Hehe...at that temperature, any silicon chip will fry. It wasn't running that hot, or else that shot wouldn't have been captured. It was an error.

 

[McElvis]

Hmmm...I thought Anand stated that the specs haven't changed since he was firt made aware of them about a year ago?

Curious...where (link) did Anand now say the specs have changed?

Joe, first page of Anand's GFFX preview -

Rumors ran rampant (as they always do) but it was none other than TSMC's 0.13-micron manufacturing process that kept NV30 from meeting its original release target, as well as its revised schedule. Just before the release of Matrox's Parhelia, NVIDIA briefed us on NV30 and promised a tape-out in May and retail availability in August. The part was sure to be a powerhouse and boasted some very impressive specifications, including a 350 - 400MHz core clock (which later turned out to be a significant understatement).

http://www.anandtech.com/video/showdoc.html?i=1779

 

[WaltC]

Hmmm...I thought Anand stated that the specs haven't changed since he was firt made aware of them about a year ago?

Curious...where (link) did Anand now say the specs have changed?

Specs wouldn't have included anything but a very general, very broad clock rate estimate, for the upper end. I would bet on between 300MHz and 400MHz. Even at 300MHz, the chip would still have had 2x the pixel fill of the nv25, and with DDRII and the same nv25 bus they'd have gotten ~60% more physical bandwidth (edit: incorrect, I realize, because then the ram bus would have been running slower than 500MHz.) I'm pretty sure in the beginning they'd never have been shooting for a fill rate which grossly exceeded the ability of their bandwidth to carry. Remember that when 9700P shipped nVidia was 90-95% done with nv30 design specs.

Personally, I subscribe to the following theory:

NVidia did originally target about 500 Mhz, but that would be on the low-k process. After the low-k didn't pan out nVidia had no choice but to produce it on the standard 0.13. Naturally, the target clock speed dropped a bit...perhaps to 9700 levles. However, after the 9700 shook up the market, they decided to "overclock" the NV30 (enter DustBbuster) to get it back up to the specs of the "original" low-k target.

I don't think that low-K would have helped them go from ~300MHz to 500MHz with normal cooling. It would have helped some, but not that much. 500MHz, obviously, became the new target after the 9700P shipped and nVidia had evaluated it. Enter Dustbuster, 12-layer pcb, etc. to handle the over voltage, etc. Early tests with the 400MHz card indicate there is even a tendency to over heat and clock throttle at 400MHz, in some cases. My estimate for the chip normally cooled and aspirated is ~300MHz (the "normal usage" clockspeed of the 5800 Ultra.)

IMO, the GF FX non-Ultra is much closer to their original design targets, although still a bit forced for current yields.

Agreed. However, my twist on this is that they didn't expect to require the FLowFX....based on a product made on 0.13 low-k dielectrics.

But from whom would they have gotten the estimate of such a possibility? According to ATI, TSMC was warning both ATI and nVidia to steer clear of the .13 micron, low-k route for awhile. So, if this was nVidia's reasoning it would have been internal to the company and not provided by the FAB. So, unless you want to consider that possibly someone in high nVidia management is irrational with an infirm grip on reality (which *chuckle* doesn't seem *that* unlikely at this point), you'd have to concede that 500MHz was a target born solely out of nVidia's estimation of what it would need to beat the 9700--and the over-clocked and over-volted 500MHz hairdryer is the best the company could do.

Somebody at nVidia has been way too free with stockholder's money, IMO, and the GF FX Ultra is the proof of it. I think they'd have been better off shipping the product as quickly as they could at the ~300MHz range and being honest about it by saying: "We look forward to intense competition with ATI with our nv35 gpus. We designed nv30 to be several steps above nv25, and we succeeded in that goal. We did not design it to compete with R300, obviously, as we began work on nv30 long before ATI shipped the 9700P." I think this approach would have been far more sane than what they are doing now, which is fooling nobody.

Even the stuff about using the post filter to do a blur and calling it "FSAA" seems to show just how far out of the reality phase these guys have fallen, IMO.

 

[demalion]

I don't get the disbelieving comments indicating that the only "post filter" possible is a "blur". EDIT: well, except that we have to take someone else's word that the screenshots don't reflect what is on screen.

If you have more color data, which they seem to have clearly indicated they do, and the post filter can access it, and I don't see why it can't, then it doesn't seem to me the blend necessarily has to be a blur.

I thought the tradeoff was more space required for the framebuffers in return for not having to process the backbuffer data down into a framebuffer the size of the screen (i.e., the processing occured at the same time as DAC output, and required no additional processing for the framebuffer creation).

 

[WaltC]

I don't get the disbelieving comments indicating that the only "post filter" possible is a "blur". EDIT: well, except that we have to take someone else's word that the screenshots don't reflect what is on screen.

If you have more color data, which they seem to have clearly indicated they do, and the post filter can access it, and I don't see why it can't, then it doesn't seem to me the blend necessarily has to be a blur.

I thought the tradeoff was more space required for the framebuffers in return for not having to process the backbuffer data down into a framebuffer the size of the screen (i.e., the processing occured at the same time as DAC output, and required no additional processing for the framebuffer creation).

3dfx pioneered this with the V3. In fact the first web screen shots taken from the card looked horrible-- worse than a V2. But the reviewers at the time (Anand included) who published the screen shots all commented on how much difference there was between the screen shots and what they saw on the screen. Later, screen-shot software was developed for the V3 which accurately grabbed the frames. Of course, the V3 used the post filter for more things than a blur--just not for FSAA, of course, since FSAA wasn't introduced until V5. 3dfx did a good job of using it with their 16/22-bit color at the time.

I am assuming that a "slight blur" is all that nVidia is doing with it--of course I don't know as I haven't seen it. It's obvious though in all of the reviews that whatever it's doing is so slight that none of the reviewers noticed the difference between what they saw on the screen and the screen shots they took--as not a one of them commented on it (as they did in the V3 case where the difference was severe.)

My contention is simply that using the post filter for this kind of an operation is not FSAA, and the fact that nVidia doesn't use the post filter at 4x FSAA and up would tend to strengthen that argument, I would think.

 

[kid_crisis]

I don't think that low-K would have helped them go from ~300MHz to 500MHz with normal cooling. It would have helped some, but not that much. 500MHz, obviously, became the new target after the 9700P shipped and nVidia had evaluated it. Enter Dustbuster, 12-layer pcb, etc. to handle the over voltage, etc. Early tests with the 400MHz card indicate there is even a tendency to over heat and clock throttle at 400MHz, in some cases. My estimate for the chip normally cooled and aspirated is ~300MHz (the "normal usage" clockspeed of the 5800 Ultra.)

Hmmm, I didn't think the NV25 was done on a TSMC copper 0.15um process. If so, the difference in conductivity from aluminum to copper must be accounted for as well:

Cu = 1.73 u-ohm-cm
Al = 2.7 u-ohm-cm

which means the resistivity of copper lines is 36% reduced from Alum, all other things being equal (which they aren't exactly, since the line widths are smaller as well, but so are the gate lengths, so it's probably still a net improvement for the total RC time constant). Anyways, that 36% series R reduction would correllate to a 56% increase in clock frequency if it were the only resistive parasitic (which it's not,you also have an output conductance in the small signal model of the swicthing device). Still an increase from 300 MHz to 400 MHz+ based on copper alone is probably reasonable.

According to ATI, TSMC was warning both ATI and nVidia to steer clear of the .13 micron, low-k route for awhile. So, if this was nVidia's reasoning it would have been internal to the company and not provided by the FAB.

It's always a difficult decision to go to a new process, and a lot more work for the designers as well. I kind of doubt TSMC was downplaying their own upcoming process in such simplistic terms however. I've never known a foundry to do this (and I've worked with several on cutting edge processes, albeit GaAs not silicon).

Even the stuff about using the post filter to do a blur and calling it "FSAA" seems to show just how far out of the reality phase these guys have fallen, IMO.

Didn't HardOCP come out and say that the IQ screenshots of the 2x FSAA modes were not representative of the actual picture on the monitor? Is that what you are talking about?

 

[gokickrocks]

Didn't HardOCP come out and say that the IQ screenshots of the 2x FSAA modes were not representative of the actual picture on the monitor?

thats what nvidia told them...

so brent went back, played a few games, and didnt notice much of an improvement IIRC

 

[WaltC]

Hmmm, I didn't think the NV25 was done on a TSMC copper 0.15um process. If so, the difference in conductivity from aluminum to copper must be accounted for as well:

Cu = 1.73 u-ohm-cm
Al = 2.7 u-ohm-cm

which means the resistivity of copper lines is 36% reduced from Alum, all other things being equal (which they aren't exactly, since the line widths are smaller as well, but so are the gate lengths, so it's probably still a net improvement for the total RC time constant). Anyways, that 36% series R reduction would correllate to a 56% increase in clock frequency if it were the only resistive parasitic (which it's not,you also have an output conductance in the small signal model of the swicthing device). Still an increase from 300 MHz to 400 MHz+ based on copper alone is probably reasonable.

Good conjecture--so why do you think it is that the MHz speed cycles back to 300MHz when the Ultra chip is, according to nVidia PR, at least, "operating normally"?

That's another question I have: I wonder if the non-Ultra cycles in MHz as well, from 400 to 300...? We do know that both clock throttle, even at 400MHz.

It's always a difficult decision to go to a new process, and a lot more work for the designers as well. I kind of doubt TSMC was downplaying their own upcoming process in such simplistic terms however. I've never known a foundry to do this (and I've worked with several on cutting edge processes, albeit GaAs not silicon).

So, I gather you think one of two things:

(1) ATI is lying and TSMC never gave them such a warning

(2) TSMC warned ATI, but not nVidia

From what ATI said at the recent stockholder's meeting, and from the output of the two companies over the last six months and the differences therein, it would appear that ATI certainly took the rather "simplistic" advice and profited from it--whereas nVidia did not. Perhaps the advice was just "too simple" for nVidia to absorb?

Didn't HardOCP come out and say that the IQ screenshots of the 2x FSAA modes were not representative of the actual picture on the monitor? Is that what you are talking about?

No....when you use the post filter it will affect the output on the screen, but it will not show up in a typical frame-buffer frame-grab. 3dfx went through the same thing with the V3 years ago, but in that case the difference between what was seen on the screen and what was frame-grabbed was extremely obvious. Later, different screen-grabbing software was made available which correctly grabbed the images, post filter adjustments included. The difference in this case that I find interesting is first of all nVidia is using the post filter only for these two FSAA modes (2x and QC) and nothing else, whereas 3dfx never used it for FSAA (even with the V5 which employed an actual 2x FSAA--and of course with the V3 there was no FSAA); also, none of the reviewers noticed a difference in the frame grabs and what was seen on the screen until *after* nVidia brought this to their attention. Which indicates a very slight difference. By contrast, each of the reviewers who reviewed the V3 prior to the screen-grab software being made available commented in the *initial review* about the differences between what they saw on the screen and what the frame-grabs portrayed--and stated they had no explanation for it. So if nVidia is using the post filter to overlay a very slight blur in these two FSAA modes when the driver is instructed to execute them, it explains why there is little performance hit, as no FSAA is actually being accomplished. This would also explain to me why nVidia has been so "excited" over the last couple of months in pushing its "2xFSAA" at the expense of every other FSAA mode(They actually do FSAA at 4x and above--post filter is not nearly enough to help there.) nVidia's never been any good with FSAA, so this doesn't surprise me. What surprises me is that the company won't admit up front how they are doing it. I suppose that a certain minority percentage simply won't care about that, but I do.

 

[demalion]

It has a performance hit, which seems to indicate more color data is being generated.

Again: If you have more color data, which they seem to have clearly indicated they do, and the post filter can access it, and I don't see why it can't, then it doesn't seem to me the blend necessarily has to be a blur.

We have no special reason to assume 2x is a blur (we really have no idea what it is). A 2x mode does not necessarily look greatly superior to no AA at decent resolution, but it has been indicated there is indeed a difference. In the face of the above information, to imply that it is doing nothing is not reasonable. It is Quincunx that blurs as part of its implemention, in order to claim to be greater than 2x. We have no reason to assume the same for 2x mode just because that is how post filtering was done prior, especially given the indications of higher fillrate usage.

 

[RussSchultz]

So, I gather you think one of two things:

(1) ATI is lying and TSMC never gave them such a warning

(2) TSMC warned ATI, but not nVidia

From what ATI said at the recent stockholder's meeting, and from the output of the two companies over the last six months and the differences therein, it would appear that ATI certainly took the rather "simplistic" advice and profited from it--whereas nVidia did not. Perhaps the advice was just "too simple" for nVidia to absorb?

Don't be an idjut. TSMC is straight forward with their customers about the risks of a new process. I'm sure that both TSMC and NVIDIA wanted it to work, and both worked hard to get it to work--it just didn't pan out in time, but both parties knew the risks.

As is always said, hind-sight is 20-20, and ATI is crowing that 'they read the signs' and their competitor didn't.

 

[stevem]

...Enter Dustbuster, 12-layer pcb, etc...

The 12 layer board is a consequence of the noise at 1GHz DDR2 (effective). Apparently there was much difficulty in this regard which necessitated this design choice @ this stage. Further 3rd hand info details 2 futher simplified board designs. No info on whether these are optimizations for NV30 or NV31/34 parts, though.

The same source hinted last year @ a 300-400MHz NV30 clock...

 

[WaltC]

So, I gather you think one of two things:

(1) ATI is lying and TSMC never gave them such a warning

(2) TSMC warned ATI, but not nVidia

From what ATI said at the recent stockholder's meeting, and from the output of the two companies over the last six months and the differences therein, it would appear that ATI certainly took the rather "simplistic" advice and profited from it--whereas nVidia did not. Perhaps the advice was just "too simple" for nVidia to absorb?

Don't be an idjut. TSMC is straight forward with their customers about the risks of a new process. I'm sure that both TSMC and NVIDIA wanted it to work, and both worked hard to get it to work--it just didn't pan out in time, but both parties knew the risks.

As is always said, hind-sight is 20-20, and ATI is crowing that 'they read the signs' and their competitor didn't.

I think you misunderstood my answer, Russ. The fellow I responded to clearly stated he thought it was unlikely that TSMC issued such a "simplistic" warning to anyone. My response needs to be read in context. It's far from idjutotic...

My original statement was that as ATI was warned about the process, most likely nVidia was, too. ATI chose to heed those warnings, nVidia did not. That seems to be the historical case of it. I didn't see ATI saying they "read signs"--maybe they did say that--but what I read that they said was that they'd been warned about the process. Of course forgotten here are the countless times nVidia has stated "the type of chip we want to do can't be done at .15 microns." Clearly ATI had a difference of opinion.

I guess the point was in the beginning a point about management. I think it's a good bet nVidia stuck it out with the process because the company didn't think something like an R300 at .15 microns was possible. Their statements certainly seem to back that up. Clear difference in not only administrative management, but also in technical ability, looks to me. ATI did something nVidia had been saying for months couldn't be done.

 

[WaltC]

...Enter Dustbuster, 12-layer pcb, etc...

The 12 layer board is a consequence of the noise at 1GHz DDR2 (effective). Apparently there was much difficulty in this regard which necessitated this design choice @ this stage. Further 3rd hand info details 2 futher simplified board designs. No info on whether these are optimizations for NV30 or NV31/34 parts, though.

The same source hinted last year @ a 300-400MHz NV30 clock...

Yes, I've said from the start that the orignal target for the chip was 300-400MHz. It wasn't until the decision was made to go to 500Mhz that the 12-layer board became necessary--noise is certainly a good enough reason... I think there were probably several, actually.

Actually having produced it however, at least at this state in the yields process, I think the nominal MHz for it with standard PCBs, voltages and cooling is ~300MHz, though.

 

[JD]

I think I read that ati would get 25% lower power draw if it went with .13 process and they risked it going with .15 process instead. It payed off for them in this case.